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is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 1 576mb ? (x9, ? x18, ? x36) ? common ? i/o ? rldram ? ? 2 ? memory ? ? features ? 533mhz ? ddr ? operation ? (1.067 ? gb/s/pin ? data ? rate) ? ? 38.4gb/s ? peak ? bandwidth ? (x36 ? at ? 533 ? mhz ? clock ? frequency) ? ? reduced ? cycle ? time ? (15ns ? at ? 533mhz) ? ? 32ms ? refresh ? (16k ? refresh ? for ? each ? bank; ? 128k ? refresh ? command ? must ? be ? issued ? in ? total ? each ? 32ms) ? ? 8 ? internal ? banks ? ? non \ multiplexed ? addresses ? (address ? multiplexing ? option ? available) ? ? sram \ type ? interface ? ? programmable ? read ? latency ? (rl), ? row ? cycle ? time, ? and ? burst ? sequence ? length ? ? balanced ? read ? and ? write ? latencies ? in ? order ? to ? optimize ? data ? bus ? utilization ? ? data ? mask ? signals ? (dm) ? to ? mask ? signal ? of ? write ? data; ? dm ? is ? sampled ? on ? both ? edges ? of ? dk. ? ? differential ? input ? clocks ? (ck, ? ck#) ? ? differential ? input ? data ? clocks ? (dkx, ? dkx#) ? ? on \ die ? dll ? generates ? ck ? edge \ aligned ? data ? and ? output ? data ? clock ? signals ? ? data ? valid ? signal ? (qvld) ? ? hstl ? i/o ? (1.5v ? or ? 1.8v ? nominal) ? ? 25 \ 60 ? matched ? impedance ? outputs ? ? 2.5v ? v ext , ? 1.8v ? v dd , ? 1.5v ? or ? 1.8v ? v ddq ? i/o ? ? on \ die ? termination ? (odt) ? r tt ? ? ieee ? 1149.1 ? compliant ? jtag ? boundary ? scan ? ? operating ? temperature: ? commercial ? (t c ? = ? 0 ? to ? +95c; ? t a ? = ? 0c ? to ? +70c), ? industrial ? (t c ? = ?\ 40c ? to ? +95c; ? t a ? = ?\ 40c ? to ? +85c) options ? ? package: ? ? 144 \ ball ? fbga ? (leaded) ? ? 144 \ ball ? fbga ? (lead \ free) ? ? configuration: ? ? 64mx9 ? ? 32mx18 ? ? 16mx36 ? ? clock ? cycle ? timing: ? speed ? grade ? \ 18 ? \ 25e ? \ 25 ? \ 33 ? \ 5 ? unit ? t rc ? 15 ? 15 ? 20 ? 20 ? 20 ? ns ? t ck ? 1.875 ? 2.5 ? 2.5 ? 3.3 ? 5 ? ns ? ? copyright ? ? ? 2012 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances ? ? rldram ? ? is ? a ? registered ? trademark ? of ? micron ? technology, ? inc. ? advanced information july 2012
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 2 1 ? package ? ball ? out ? and ? description ? 1.1 ? 576mb ? (64mx9) ? common ? i/o ? bga ? ball \ out ? (top ? view) ? ? ? 1 2 3 4 5 6 7 8 9 10 11 12 a vref vss vext vss vss vext tms tck b vdd dnu 3 dnu 3 vss q vss q dq0 dnu 3 vdd c vtt dnu 3 dnu 3 vddq vddq dq1 dnu 3 vtt d a22 1 dnu 3 dnu 3 vss q vss q qk0# qk0 vss e a21 dnu 3 dnu 3 vddq vddq dq2 dnu 3 a20 f a5 dnu 3 dnu 3 vss q vss q dq3 dnu 3 qvld g a8 a6 a7 vdd vdd a2 a1 a0 h ba2 a9 vss vss vss vss a4 a3 j nf 2 nf 2 vdd vdd vdd vdd ba0 ck k dk dk# vdd vdd vdd vdd ba1 ck# l ref# cs# vss vss vss vss a14 a13 m we# a16 a17 vdd vdd a12 a11 a10 n a18 dnu 3 dnu 3 vss q vss q dq4 dnu 3 a19 p a15 dnu 3 dnu 3 vddq vddq dq5 dnu 3 dm r vss dnu 3 dnu 3 vss q vss q dq6 dnu 3 vss t vtt dnu 3 dnu 3 vddq vddq dq7 dnu 3 vtt u vdd dnu 3 dnu 3 vss q vss q dq8 dnu 3 vdd v vref zq vext vss vss vext tdo tdi symbol description ball ? count vdd supply ? voltage 16 vss ground 16 vddq dq ? power ? supply 8 vssq dq ? ground 12 vext supply ? voltage 4 vref reference ? voltage 2 vtt termination ? voltage 4 a* address ?\? a0 \ 22 23 ba* banks ?\? ba0 \ 23 dq* i/o 9 dk* input ? data ? clock(differential ? inputs) 2 qk* output ? data ? clocks(outputs) 2 ck* input ? clocks ? (ck, ? ck#) 2 dm input ? data ? mask 1 cs#,we#,ref# command ? control ? pins 3 zq external ? impedance ? (25?60 )1 qvld data ? valid 1 dnu,nf do ? not ? use, ? no ? function 31 t* jtag ?\? tck,tms,tdo,tdi 4 total 144 notes: 1) reserved for future use. this may optionally be connected to gnd. 2) reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. 3) no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to gnd. 4) do not use. this signal is internally connected and has parasitic characteristics of a i/o. this may optionally be connected to gnd. note that if odt is enabled, these pins will be connected to vtt. notes: 1) reserved for future use. this may optionally be connected to gnd. 2) reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. notes: 1. ? reserved ? for ? future ? use. ? this ? signal ? is ? not ? connected. 2. ? no ? function. ? this ? signal ? is ? internally ? connected ? and ? has ? parasitic ? characteristics ? of ? a ? clock ? input ? signal. ? this ? may ? optionally ? be ? connected ? to ? gnd. 3. ? do ? not ? use. ? this ? signal ? is ? internally ? connected ? and ? has ? parasitic ? characteristics ? of ? a ? i/o. ? this ? may ? optionally ? be ? connected ? to ? gnd. ? note ? that ? if ? odt ? is ? enabled, ? these ? pins ? are ? high \ z.
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 3 ? ? 1.2 ? 576mb ? (32mx18) ? common ? i/o ? bga ? ball \ out ? (top ? view) ? ? ? 1 2 3 4 5 6 7 8 9 10 11 12 a vref vss vext vss vss vext tms tck b vdd dnu 4 dq4 vss q vss q dq0 dnu 4 vdd c vtt dnu 4 dq5 vddq vddq dq1 dnu 4 vtt d a22 1 dnu 4 dq6 vss q vss q qk0# qk0 vss e a21 2 dnu 4 dq7 vddq vddq dq2 dnu 4 a20 f a5 dnu 4 dq8 vss q vss q dq3 dnu 4 qvld g a8 a6 a7 vdd vdd a2 a1 a0 h ba2 a9 vss vss vss vss a4 a3 j nf 3 nf 3 vdd vdd vdd vdd ba0 ck k dk dk# vdd vdd vdd vdd ba1 ck# l ref# cs# vss vss vss vss a14 a13 m we# a16 a17 vdd vdd a12 a11 a10 n a18 dnu 4 dq14 vss q vss q dq9 dnu 4 a19 p a15 dnu 4 dq15 vddq vddq dq10 dnu 4 dm r vss qk1 qk1# vssq vssq dq11 dnu 4 vss t vtt dnu 4 dq16 vddq vddq dq12 dnu 4 vtt u vdd dnu 4 dq17 vss q vss q dq13 dnu 4 vdd v vref zq vext vss vss vext tdo tdi symbol description ball ? count vdd supply ? voltage 16 vss ground 16 vddq dq ? power ? supply 8 vssq dq ? ground 12 vext supply ? voltage 4 vref reference ? voltage 2 vtt termination ? voltage 4 a* address ?\? a0 \ 22 23 ba* banks ?\? ba0 \ 23 dq* i/o 18 dk* input ? data ? clock(differential ? inputs) 2 qk* output ? data ? clocks(outputs) 4 ck* input ? clocks ? (ck, ? ck#) 2 dm input ? data ? mask 1 cs#,we#,ref# command ? control ? pins 3 zq external ? impedance ? (25?60 )1 qvld data ? valid 1 dnu,nf do ? not ? use, ? no ? function 20 t* jtag ?\? tck,tms,tdo,tdi 4 total 144 notes: 1) reserved for future use. this may optionally be connected to gnd. 2) reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. 3) no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to gnd. 4) do not use. this signal is internally connected and has parasitic characteristics of a i/o. this may optionally be connected to gnd. note that if odt is enabled, these pins will be connected to vtt. notes: 1) reserved for future use. this may optionally be connected to gnd. 2) reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. 3) no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to gnd. 4) do not use. this signal is internally connected and has parasitic characteristics of a i/o. this may optionally be connected to gnd. note that if odt is enabled, these pins will be connected to vtt. notes: 1. ? reserved ? for ? future ? use. ? this ? may ? optionally ? be ? connected ? to ? gnd. 2. ? reserved ? for ? future ? use. ? this ? signal ? is ? internally ? connected ? and ? has ? parasitic ? characteristics ? of ? an ? address ? input ? signal. ? this ? may ? optionally ? be ? connected ? to ? gnd. 3. ? no ? function. ? this ? signal ? is ? internally ? connected ? and ? has ? parasitic ? characteristics ? of ? a ? clock ? input ? signal. ? this ? may ? optionally ? be ? connected ? to ? gnd. 4. ? do ? not ? use. ? this ? signal ? is ? internally ? connected ? and ? has ? parasitic ? characteristics ? of ? a ? i/o. ? this ? may ? optionally ? be ? connected ? to ? gnd. ? note ? that ? if ? odt ? is ? enabled, ? these ? pins ? are ? high \ z.
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 4 1.3 ? 576mb ? (16mx36) ? common ? i/o ? bga ? ball \ out ? (top ? view) ? 1 2 3 4 5678 9 10 11 12 a vref vss vext vss vss vext tms tck b vdd dq8 dq9 vssq vssq dq1 dq0 vdd c vtt dq10 dq11 vddq vddq dq3 dq2 vtt d a22 1 dq12 dq13 vssq vssq qk0# qk0 vss e a21 2 dq14 dq15 vddq vddq dq5 dq4 a20 2 f a5 dq16 dq17 vssq vssq dq7 dq6 qvld g a8 a6 a7 vdd vdd a2 a1 a0 h ba2 a9 vss vss vss vss a4 a3 j dk0 dk0# vdd vdd vdd vdd ba0 ck k dk1 dk1# vdd vdd vdd vdd ba1 ck# l ref# cs# vss vss vss vss a14 a13 m we# a16 a17 vdd vdd a12 a11 a10 n a18 dq24 dq25 vssq vssq dq35 dq34 a19 p a15 dq22 dq23 vddq vddq dq33 dq32 dm r vss qk1 qk1# vssq vssq dq31 dq30 vss t vtt dq20 dq21 vddq vddq dq29 dq28 vtt u vdd dq18 dq19 vssq vssq dq27 dq26 vdd v vref zq vext vss vss vext tdo tdi symbol description ball ? count vdd supply ? voltage 16 vss ground 16 vddq dq ? power ? supply 8 vssq dq ? ground 12 vext supply ? voltage 4 vref reference ? voltage 2 vtt termination ? voltage 4 a* address ?\? a0 \ 22 23 ba* banks ?\? ba0 \ 23 dq* i/o 36 dk* input ? data ? clock(differential ? inputs) 4 qk* output ? data ? clocks(outputs) 4 ck* input ? clocks ? (ck, ? ck#) 2 dm input ? data ? mask 1 cs#,we#,ref# command ? control ? pins 3 zq external ? impedance ? (25?60 )1 qvld data ? valid 1 dnu do ? not ? use 0 t* jtag ?\? tck,tms,tdo,tdi 4 total 144 notes: 1. ? reserved ? for ? future ? use. ? this ? may ? optionally ? be ? connected ? to ? gnd. 2. ? reserved ? for ? future ? use. ? this ? signal ? is ? internally ? connected ? and ? has ? parasitic ? characteristics ? of ? an ? address ? input ? signal. ? this ? may ? optionally ? be ? connected ? to ? gnd. ? ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 5 1.4 ? ball ? descriptions ? symbol ? type ? description ? a* ? input ? address ? inputs: ? defines ? the ? row ? and ? column ? addresses ? for ? read ? and ? write ? operations. ? during ? a ? mode ? register ? set, ? the ? address ? inputs ? define ? the ? register ? settings. ? they ? are ? sampled ? at ? the ? rising ? edge ? of ? ck. ? ba* ? input ? bank ? address ? inputs: ? selects ? to ? which ? internal ? bank ? a ? command ? is ? being ? applied ? to. ? ck, ? ck# ? input ? input ? clock: ? ck ? and ? ck# ? are ? differential ? input ? clocks. ? addresses ? and ? commands ? are ? latched ? on ? the ? rising ? edge ? of ? ck. ? ck# ? is ? ideally ? 180 ? degrees ? out ? of ? phase ? with ? ck. ? cs# ? input ? chip ? select: ? cs# ? enables ? the ? command ? decoder ? when ? low ? and ? disables ? it ? when ? high. ? when ? the ? command ? decoder ? is ? disabled, ? new ? commands ? are ? ignored, ? but ? internal ? operations ? continue. ? dq* ? i/o ? data ? input: ? the ? dq ? signals ? form ? the ? data ? bus. ? during ? read ? commands, ? the ? data ? is ? referenced ? to ? both ? edges ? of ? qk*. ? during ? write ? commands, ? the ? data ? is ? sampled ? at ? both ? edges ? of ? dk. ? dk*, ? dk*# ? input ? input ? data ? clock: ? dk* ? and ? dk*# ? are ? the ? differential ? input ? data ? clocks. ? all ? input ? data ? is ? referenced ? to ? both ? edges ? of ? dk*. ? dk*# ? is ? ideally ? 180 ? degrees ? out ? of ? phase ? with ? dk*. ? for ? the ? x36 ? device, ? dq0?dq17 ? are ? referenced ? to ? dk0 ? and ? dk0# ? and ? dq18?dq35 ? are ? referenced ? to ? dk1 ? and ? dk1#. ? for ? the ? x9 ? and ? x18 ? devices, ? all ? dq* ? are ? referenced ? to ? dk ? and ? dk#. ? all ? dk* ? and ? dk*# ? pins ? must ? always ? be ? supplied ? to ? the ? device. ? dm ? input ? input ? data ? mask: ? the ? dm ? signal ? is ? the ? input ? mask ? signal ? for ? write ? data. ? input ? data ? is ? masked ? when ? dm ? is ? sampled ? high. ? dm ? is ? sampled ? on ? both ? edges ? of ? dk ? (dk1 ? for ? the ? x36 ? configuration). ? tie ? signal ? to ? ground ? if ? not ? used. ? tck ? input ? ieee ? 1149.1 ? clock ? input: ? this ? ball ? must ? be ? tied ? to ? v ss ? if ? the ? jtag ? function ? is ? not ? used. ? tms,tdi ? input ? ieee ? 1149.1 ? test ? inputs: ? these ? balls ? may ? be ? left ? as ? no ? connects ? if ? the ? jtag ? function ? is ? not ? used. we#, ? ref# ? input ? command ? inputs: ? sampled ? at ? the ? positive ? edge ? of ? ck, ? we# ? and ? ref# ? define ? (together ? with ? cs#) ? the ? command ? to ? be ? executed. ? v ref ? input ? input ? reference ? voltage: ? nominally ? v dd q /2. ? provides ? a ? reference ? voltage ? for ? the ? input ? buffers. ? zq ? i/o ? external ? impedance ? (25 ? 60 ): this ? signal ? is ? used ? to ? tune ? the ? device ? outputs ? to ? the ? system ? data ? bus ? impedance. ? dq ? output ? impedance ? is ? set ? to ? 0.2 ? ? rq, ? where ? rq ? is ? a ? resistor ? from ? this ? signal ? to ? ground. ? connecting ? zq ? to ? gnd ? invokes ? the ? minimum ? impedance ? mode. ? qk*, ? qk*# ? output ? output ? data ? clocks: ? qk* ? and ? qk*# ? are ? opposite ? polarity, ? output ? data ? clocks. ? they ? are ? free ? running, ? and ? during ? reads, ? are ? edge \ aligned ? with ? data ? output ? from ? the ? memory. ? qk*# ? is ? ideally ? 180 ? degrees ? out ? of ? phase ? with ? qk*. ? for ? the ? x36 ? device, ? qk0 ? and ? qk0# ? are ? aligned ? with ? dq0 \ dq17, ? and ? qk1 ? and ? qk1# ? are ? aligned ? with ? dq18 \ dq35. ? for ? the ? x18 ? device, ? qk0 ? and ? qk0# ? are ? aligned ? with ? dq0 \ dq8, ? while ? qk1 ? and ? qk1# ? are ? aligned ? with ? q9 \ q17. ? for ? the ? x9 ? device, ? all ? dqs ? are ? aligned ? with ? qk0 ? and ? qk0#. ? qvld ? output ? data ? valid: ? the ? qvld ? pin ? indicates ? valid ? output ? data. ? qvld ? is ? edge \ aligned ? with ? qk* ? and ? qk*#. tdo ? output ? ieee ? 1149.1 ? test ? output: ? jtag ? output. ? this ? ball ? may ? be ? left ? as ? no ? connect ? if ? the ? jtag ? function ? is ? not ? used. ? v dd ? supply ? power ? supply: ? nominally, ? 1.8v. v dd q ? supply ? dq ? power ? supply: ? nominally, ? 1.5v ? or ? 1.8v. ? isolated ? on ? the ? device ? for ? improved ? noise ? immunity. v ext ? supply ? power ? supply: ? nominally, ? 2.5v. ? v ss ? supply ? ground. ? v ss q ? supply ? dq ? ground: ? isolated ? on ? the ? device ? for ? improved ? noise ? immunity. ? v tt ? supply ? power ? supply: ? isolated ? termination ? supply. ? nominally, ? v dd q /2. ? a22 ?\? reserved ? for ? future ? use: ? this ? signal ? is ? not ? connected ? and ? can ? be ? connected ? to ? ground. dnu ?\? do ? not ? use: ? these ? balls ? may ? be ? connected ? to ? ground. ? note ? that ? if ? odt ? is ? enabled, ? these ? pins ? are ? high \ z. nf ?\? no ? function: ? these ? balls ? can ? be ? connected ? to ? ground. ??? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 6 2 ? electrical ? specifications ? 2.1 ? absolute ? maximum ? ratings ? item ? min ? max ? units ? i/o ? voltage ? ? 0.3 ? v dd q ? + ? 0.3 ? v voltage ? on ? v ext ? supply ? relative ? to ? v ss ? ? 0.3 ? + ? 2.8 ? v voltage ? on ? v dd ? supply ? relative ? to ? v ss ? ? 0.3 ? + ? 2.1 ? v voltage ? on ? v dd q ? supply ? relative ? to ? v ss ? ? 0.3 ? + ? 2.1 ? v note: ? stress ? greater ? than ? those ? listed ? in ? this ? table ? may ? cause ? permanent ? damage ? to ? the ? device. ? this ? is ? a ? stress ? rating ? only ? and ? functional ? operation ? of ? the ? device ? at ? these ? or ? any ? other ? conditions ? above ? those ? indicated ? in ? the ? operational ? sections ? of ? this ? specification ? is ? not ? implied. ? exposure ? to ? absolute ? maximum ? rating ? conditions ? for ? extended ? periods ? may ? affect ? reliability. ? ? 2.2 ? dc ? electrical ? characteristics ? and ? operating ? conditions ? description ? conditions ? symbol ? min ? max ? units ? notes ? supply ? voltage ? ? v ext ? 2.38 ? 2.63 ? v ?? supply ? voltage ? ? v dd ? 1.7 ? 1.9 ? v ? 2 ? isolated ? output ? buffer ? supply ? ? v dd q ? 1.4 ? vdd ? v ? 2,3 ? reference ? voltage ? ? v ref ? 0.49 ? x ? v dd q ? 0.51 ? x ? v dd q ? v ? 4,5,6 ? termination ? voltage ? ? v tt ? 0.95 ? x ? v ref ? 1.05 ? x ? v ref ? v ? 7,8 ? input ? high ? voltage ? ? v ih ? v ref ? + ? 0.1 ? v dd q ? + ? 0.3 ? v ? 2 ? input ? low ? voltage ? ? v il ? v ssq ? ? 0.3 ? v ref ? ? ? 0.1 ? v ? 2 ? output ? high ? current ? v oh ? = ? v ddq /2 ? i oh ? (v ddq /2)/ (1.15 ? x ? rq/5) ? (v ddq /2)/ ? (0.85 ? x ? rq/5) ? a ? 9, ? 10, ? 11 ? output ? low ? current ? v ol ? = ? v ddq /2 ? i ol ? (v ddq /2)/ (1.15 ? x ? rq/5) ? (v ddq /2)/ ? (0.85 ? x ? rq/5) ? a ? 9, ? 10, ? 11 ? clock ? input ? leakage ? current ? 0v ?? v in ?? v dd ? i lc ? ? 5 ? 5 ? a ?? input ? leakage ? current ? 0v ?? v in ?? v dd ? i li ? ? 5 ? 5 ? a ?? output ? leakage ? current ? 0v ?? v in ?? v dd q ? i lo ? ? 5 ? 5 ? a ?? reference ? voltage ? current ?? i ref ? ? 5 ? 5 ? a ?? notes: ? 1. all ? voltages ? referenced ? to ? v ss ? (gnd). ? 2. overshoot: ? v ih ? (ac) ?? v dd ? + ? 0.7v ? for ? t ?? t ck /2. ? undershoot: ? v il ? (ac) ?? ?0.5v ? for ? t ?? t ck /2. ? during ? normal ? operation, ? v ddq ? must ? not ? exceed ? v dd . ? control ? input ? signals ? may ? not ? have ? pulse ? widths ? less ? than ? t ck /2 ? or ? operate ? at ? frequencies ? exceeding ? t ck ? (max). ? 3. v ddq ? can ? be ? set ? to ? a ? nominal ? 1.5v ? ? 0.1v ? or ? 1.8v ? ? 0.1v ? supply. ? 4. typically ? the ? value ? of ? v ref ? is ? expected ? to ? be ? 0.5 ? x ? v ddq ? of ? the ? transmitting ? device. ? v ref ? is ? expected ? to ? track ? variations ? in ? v ddq . ? 5. peak \ to \ peak ? ac ? noise ? on ? v ref ? must ? not ? exceed ? 2 ? percent ? v ref ? (dc). ? 6. v ref ? is ? expected ? to ? equal ? v ddq /2 ? of ? the ? transmitting ? device ? and ? to ? track ? variations ? in ? the ? dc ? level ? of ? the ? same. ? peak \ to \ peak ? noise ? (non \ common ? mode) ? on ? v ref ? may ? not ? exceed ? 2 ? percent ? of ? the ? dc ? value. ? thus, ? from ? v ddq /2, ? v ref ? is ? allowed ? 2 ? percent ? v ddq /2 ? for ? dc ? error ? and ? an ? additional ? 2 ? percent ? v ddq /2 ? for ? ac ? noise. ? this ? measurement ? is ? to ? be ? taken ? at ? the ? nearest ? v ref ? bypass ? capacitor. ? 7. v tt ? is ? expected ? to ? be ? set ? equal ? to ? v ref ? and ? must ? track ? variations ? in ? the ? dc ? level ? of ? v ref . ? 8. on \ die ? termination ? may ? be ? selected ? using ? mode ? register ? a9 ? (for ? non \ multiplexed ? address ? mode) ? or ? ax9 ? (for ? multiplexed ? address ? mode). ? a ? resistance ? r tt ? from ? each ? data ? input ? signal ? to ? the ? nearest ? v tt ? can ? be ? enabled. ? r tt ? = ? 125?185 ? at ? 95c ? t c . ? 9. i oh ? and ? i ol ? are ? defined ? as ? absolute ? values ? and ? are ? measured ? at ? v ddq ? /2. ? i oh ? flows ? from ? the ? device, ? i ol ? flows ? into ? the ? device. ? 10. if ? mrs ? bit ? a8 ? or ? ax8 ? is ? 0, ? use ? rq ? = ? 250 ? in ? the ? equation ? in ? lieu ? of ? presence ? of ? an ? external ? impedance ? matched ? resistor. ? ? 2.3 ? capacitance ? (t a ? = ? 25 ? c, ? f ? = ? 1mhz) ? parameter ? symbol ? test ? conditions ? min ? max ? units ? address ? / ? control ? input ? capacitance ? c in ? v in =0v ? 1.5 ? 2.5 ? pf ? i/o, ? output, ? other ? capacitance ? (dq, ? dm, ? qk, ? qvld) ? c io ? v io =0v ? 3.5 ? 5.0 ? pf ? clock ? input ? capacitance ? c clk ? v clk =0v ? 2.0 ? 3.0 ? pf ? jtag ? pins ? c j ? v j =0v ? 2.0 ? 5.0 ? pf ? note. ? these ? parameters ? are ? not ? 100% ? tested ? and ? capacitance ? is ? not ? tested ? on ? zq ? pin. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 7 2.4 ? operating ? conditions ? and ? maximum ? limits ? description ? condition ? symbol ?\ 18 ?\ 25e ?\ 25 ?\ 33 ? \ 5 ? units ? standby ? current ? t ck ? = ? idle; ? all ? banks ? idle; ? no ? inputs ? toggling ? isb1(v dd ) ? x9/x18 ? 55 ? 53 ? 48 ? 48 ? 48 ? ma ? ? isb1(v dd ) ? x36 ? 55 ? 53 ? 48 ? 48 ? 48 ? isb1(v ext ) ? 5 ? 5 ? 5 ? 5 ? 5 ? active ? standby ? current ? cs# ? =1; ? no ? commands; ? bank ? address ? incremented ? and ? half ? address/data ? change ? once ? every ? 4 ? clock ? cycles ? isb2(v dd ) ? x9/x18 ? 365 ? 293 ? 288 ? 233 ? 189 ? ma ? ? isb2(v dd ) ? x36 ? 365 ? 293 ? 288 ? 233 ? 189 ? isb2(v ext ) ? 5 ? 5 ? 5 ? 5 ? 5 ? operational ? current ? bl=2; ? sequential ? bank ? access; ? bank ? transitions ? once ? every ? t rc ; ? half ? address ? transitions ? once ? every ? t rc ; ? read ? followed ? by ? write ? sequence; ? continuous ? data ? during ? write ? commands ? idd1(v dd ) ? x9/x18 ? 465 ? 380 ? 348 ? 305 ? 255 ? ma ? ? idd1(v dd ) ? x36 ? 485 ? 400 ? 374 ? 343 ? 292 ? idd1(v ext ) ? 15 ? 15 ? 15 ? 13 ? 13 ? bl ? = ? 4; ? sequential ? bank ? access; ? bank ? transitions ? once ? every ? t rc ; ? half ? address ? transitions ? once ? every ? trc; ? read ? followed ? by ? write ? sequence; ? continuous ? data ? during ? write ? commands ? idd2(v dd ) ? x9/x18 ? 475 ? 400 ? 362 ? 319 ? 269 ? ma ? ? idd2(v dd ) ? x36 ? 510 ? 425 ? 418 ? 389 ? 339 ? idd2(v ext ) ? 15 ? 15 ? 15 ? 13 ? 13 ? bl ? = ? 8; ? sequential ? bank ? access; ? bank ? transitions ? once ? every ? t rc ; ? half ? address ? transitions ? once ? every ? trc; ? read ? followed ? by ? write ? sequence; ? continuous ? data ? during ? write ? commands ? idd3 ? (v dd ) ? x9/x18 ? 505 ? 430 ? 408 ? 368 ? 286 ? ma ? ? idd3 ? (v dd ) ? x36 ? 625 ? 540 ? 460 ? 425 ? 425 ? idd3(v ext ) ? 20 ? 20 ? 20 ? 18 ? 18 ? burst ? refresh ? current ? eight \ bank ? cyclic ? refresh; ? continuous ? address/data; ? command ? bus ? remains ? in ? refresh ? for ? all ? eight ? banks ? iref1(v dd ) ? x9/x18 ? 995 ? 790 ? 785 ? 615 ? 430 ? ma ? ? iref1(v dd ) ? x36 ? 995 ? 915 ? 785 ? 615 ? 430 ? iref1(v ext ) ? 80 ? 80 ? 80 ? 70 ? 70 ? distributed ? refresh ? current ? single \ bank ? refresh; ? sequential ? bank ? access; ? half ? address ? transitions ? once ? every ? t rc , ? continuous ? data ? iref2(v dd ) ? x9/x18 ? 425 ? 330 ? 325 ? 267 ? 221 ? ma ? ? iref2(v dd ) ? x36 ? 425 ? 390 ? 326 ? 281 ? 227 ? iref2(v ext ) ? 20 ? 20 ? 20 ? 18 ? 18 ? operating ? burst ? write ? current ? bl=2; ? cyclic ? bank ? access; ? half ? of ? address ? bits ? change ? every ? clock ? cycle; ? continuous ? data; ? measurement ? is ? taken ? during ? continuous ? write ? idd2w(v dd ) ? x9/x18 ? 1335 ? 980 ? 970 ? 819 ? 597 ? ma ? ? idd2w(v dd ) ? x36 ? 1545 ? 1105 ? 990 ? 914 ? 676 ? idd2w(v ext ) ? 50 ? 50 ? 50 ? 40 ? 40 ? bl=4; ? cyclic ? bank ? access; ? half ? of ? address ? bits ? change ? every ? 2 ? clock ? cycles; ? continuous ? data; ? measurement ? is ? taken ? during ? continuous ? write ? idd4w(v dd ) ? x9/x18 ? 985 ? 785 ? 779 ? 609 ? 439 ? ma ? ? idd4w(v dd ) ? x36 ? 1185 ? 887 ? 882 ? 790 ? 567 ? idd4w(v ext ) ? 30 ? 30 ? 30 ? 25 ? 25 ? bl=8; ? cyclic ? bank ? access; ? half ? of ? address ? bits ? change ? every ? 4 ? clock ? cycles; ? continuous ? data; ? measurement ? is ? taken ? during ? continuous ? write ? idd8w(v dd ) ? x9/x18 ? 770 ? 675 ? 668 ? 525 ? 364 ? ma ? ? idd8w(v dd ) ? x36 ? 1095 ? 755 ? 750 ? 580 ? 580 ? idd8w(v ext ) ? 30 ? 30 ? 30 ? 25 ? 25 ? operating ? burst ? read ? current ? bl=2; ? cyclic ? bank ? access; ? half ? of ? address ? bits ? change ? every ? clock ? cycle; ? measurement ? is ? taken ? during ? continuous ? read ? idd2r(v dd ) ? x9/x18 ? 1225 ? 940 ? 935 ? 735 ? 525 ? ma ? ? idd2r(v dd ) ? x36 ? 1270 ? 995 ? 990 ? 795 ? 565 ? idd2r(v ext ) ? 50 ? 50 ? 50 ? 40 ? 40 ? bl=4; ? cyclic ? bank ? access; ? half ? of ? address ? bits ? change ? every ? clock ? cycle; ? measurement ? is ? taken ? during ? continuous ? read ? idd4r(v dd ) ? x9/x18 ? 860 ? 685 ? 680 ? 525 ? 380 ? ma ? ? idd4r(v dd ) ? x36 ? 920 ? 735 ? 730 ? 660 ? 455 ? idd4r(v ext ) ? 30 ? 30 ? 30 ? 25 ? 25 ? bl=8; ? cyclic ? bank ? access; ? half ? of ? address ? bits ? change ? every ? clock ? cycle; ? measurement ? is ? taken ? during ? continuous ? read ? idd8r(v dd ) ? x9/x18 ? 655 ? 575 ? 570 ? 450 ? 310 ? ma ? ? idd8r(v dd ) ? x36 ? 855 ? 665 ? 660 ? 505 ? 505 ? idd8r(v ext ) ? 30 ? 30 ? 30 ? 25 ? 25 ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 8 notes: ? 1) idd ? specifications ? are ? tested ? after ? the ? device ? is ? properly ? initialized. ? +0c ?? t c ?? +95c; ? +1.7v ?? v dd ?? +1.9v, ? +2.38v ?? v ext ?? +2.63v, ? +1.4v ?? v ddq ?? v dd , ? v ref ? = ? v ddq /2. ? 2) t ck ? = ? t dk ? = ? min, ? t rc ? = ? min. ? 3) definitions ? for ? idd ? conditions: ? a. low ? is ? defined ? as ? v in ? ? v il (ac) ? max. ? b. high ? is ? defined ? as ? v in ?? v ih (ac) ? min. ? c. stable ? is ? defined ? as ? inputs ? remaining ? at ? a ? high ? or ? low ? level. ? d. floating ? is ? defined ? as ? inputs ? at ? v ref ? = ? v ddq /2. ? e. continuous ? data ? is ? defined ? as ? half ? the ? d ? or ? q ? signals ? changing ? between ? high ? and ? low ? every ? half ? clock ? cycle ? (twice ? per ? clock). ? f. continuous ? address ? is ? defined ? as ? half ? the ? address ? signals ? changing ? between ? high ? and ? low ? every ? clock ? cycle ? (once ? per ? clock). ? g. sequential ? bank ? access ? is ? defined ? as ? the ? bank ? address ? incrementing ? by ? one ? every ? t rc . ? h. cyclic ? bank ? access ? is ? defined ? as ? the ? bank ? address ? incrementing ? by ? one ? for ? each ? command ? access. ? for ? bl ? = ? 2 ? this ? is ? every ? clock, ? for ? bl ? = ? 4 ? this ? is ? every ? other ? clock, ? and ? for ? bl ? = ? 8 ? this ? is ? every ? fourth ? clock. ? 4) cs# ? is ? high ? unless ? a ? read, ? write, ? aref, ? or ? mrs ? command ? is ? registered. ? cs# ? never ? transitions ? more ? than ? once ? per ? clock ? cycle. ? 5) idd ? parameters ? are ? specified ? with ? odt ? disabled. ? 6) tests ? for ? ac ? timing, ? idd, ? and ? electrical ? ac ? and ? dc ? characteristics ? may ? be ? conducted ? at ? nominal ? reference/supply ? voltage ? levels, ? but ? the ? related ? specifications ? and ? device ? operations ? are ? tested ? for ? the ? full ? voltage ? range ? specified. ? 7) idd ? tests ? may ? use ? a ? v il \ to \ v ih ? swing ? of ? up ? to ? 1.5v ? in ? the ? test ? environment, ? but ? input ? timing ? is ? still ? referenced ? to ? v ref ? (or ? to ? the ? crossing ? point ? for ? ck/ck#). ? parameter ? specifications ? are ? tested ? for ? the ? specified ? ac ? input ? levels ? under ? normal ? use ? conditions. ? the ? minimum ? slew ? rate ? for ? the ? input ? signals ? used ? to ? test ? the ? device ? is ? 2 ? v/ns ? in ? the ? range ? between ? v il (ac) ? and ? v ih (ac). ? ? 2.5 ? recommended ? ac ? operating ? conditions ? (+0c ?? t c ?? +95c; ? +1.7v ?? v dd ?? +1.9v, ? unless ? otherwise ? noted.) ? parameter ? symbol ? min ? max ? units ? input ? high ? voltage ? v ih (ac) v ref + ? 0.2 \? v input ? low ? voltage ? v il (ac) ?\? v ref ? ? ? 0.2 ? v ? notes: ?? 1. overshoot: ? v ih ? (ac) ?? v ddq ? + ? 0.7v ? for ? t ?? t ck /2 ? 2. undershoot: ? v il ? (ac) ?? ? ? 0.5v ? for ? t ?? t ck /2 ? 3. control ? input ? signals ? may ? not ? have ? pulse ? widths ? less ? than ? t ckh (min) ? or ? operate ? at ? cycle ? rates ? less ? than ? t ck (min.). ? ? 2.6 ? temperature ? and ? thermal ? impedance ? temperature ? limits ? parameter ? symbol ? min ? max ? units ? reliability ? junction ? temperature ? 1 ? t j ? 0 ? +110 ? c ? operating ? junction ? temperature ? 2 ? t j ? 0 ? +100 ? c ? operating ? case ? temperature ? 3 ? t c ? 0 ? +95 ? c ? notes: ? 1. temperatures ? greater ? than ? 110c ? may ? cause ? permanent ? damage ? to ? the ? device. ? this ? is ? a ? stress ? rating ? only ? and ? functional ? operation ? of ? the ? device ? at ? or ? above ? this ? is ? not ? implied. ? exposure ? to ? absolute ? maximum ? rating ? conditions ? for ? extended ? periods ? may ? affect ? reliability ? of ? the ? part. ? 2. junction ? temperature ? depends ? upon ? cycle ? time, ? loading, ? ambient ? temperature, ? and ? airflow. ? 3. max ? operating ? case ? temperature; ? t c ? is ? measured ? in ? the ? center ? of ? the ? package. ? device ? functionality ? is ? not ? guaranteed ? if ? the ? device ? exceeds ? maximum ? t c ? during ? operation. ? ? thermal ? resistance ? package ? substrate ? theta \ j a ?? (airflow ? = ? 0m/s) ? theta \ j a ? (airflow ? = ? 1m/s) ? theta \ j a ? (airflow ? = ? 2m/s) ? ? theta \ jc ? unit ? 144 \ ball ? fbga ? 4 \ layer ? 20.6 ? 19.1 ? 17.2 ? 2.4 ? c/w ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 9 2.7 ? ac ? electrical ? characteristics ? (1, ? 2, ? 3, ? 4) ? description ? symbol ? \ 18 ? (1.875ns ? @t rc =15ns) ? \ 25e ? (2.5ns ? @t rc =15ns) ? \ 25 ? (2.5ns ? @t rc =20ns) ? \ 33 ? (3.3ns ? @t rc =20ns) ? \ 5 ? (5ns ? @t rc =20ns) ? units ? min ? max ? min ? max ? min ? max ? min ? max ? min ? max ?? input ? clock ? cycle ? time ? t ck ? 1.875 ? 2.7 ? 2.5 ? 5.7 ? 2.5 ? 5.7 ? 3.3 ? 5.7 ? 5.0 ? 5.7 ? ns ? input ? data ? clock ? cycle ? time ?? t dk ? tck ? ? ? tck ? ? ? tck ? ? ? tck ? ? ? tck ? ? ? ns ? clock ? jitter: ? period ? (5, ? 6) ? t jitper ? ?100 ? 100 ? ?150 ? 150 ? ?150 ? 150 ? ?200 ? 200 ? ?250 ? 250 ? ps ? clock ? jitter: ?? cycle \ to \ cycle ? t jitcc ? ? ? 200 ? ? ? 300 ? ? ? 300 ? ? ? 400 ? ? ? 500 ? ps ? clock ? high ? time ? t ckh /t dkh ? 0.45 ? 0.55 ? 0.45 ? 0.55 ? 0.45 ? 0.55 ? 0.45 ? 0.55 ? 0.45 ? 0.55 ? t ck ? clock ? low ? time ? t ckl /t dkl ? 0.45 ? 0.55 ? 0.45 ? 0.55 ? 0.45 ? 0.55 ? 0.45 ? 0.55 ? 0.45 ? 0.55 ? t ck ? clock ? to ? input ? data ?? clock ? t ckdk ? ?0.3 ? 0.3 ? ?0.45 ? 0.5 ? ?0.45 ? 0.5 ? ?0.45 ? 1.2 ? ?0.3 ? 1.5 ? ns ? mode ? register ? set ?? cycle ? time ? to ? any ? command ? t mrsc ? 6 ? ? ? 6 ? ? ? 6 ? ? ? 6 ? ? ? 6 ? ? ? t ck ? address/command ?? and ? input ? setup ? time ? t as /t cs ? 0.3 ? ? ? 0.4 ? ? ? 0.4 ? ? ? 0.5 ? ? ? 0.8 ? ? ? ns ? data \ in ? and ? data ?? mask ? to ? dk ? setup ? time ? t ds ? 0.17 ? ? ? 0.25 ? ? ? 0.25 ? ? ? 0.3 ? ? ? 0.4 ? ? ? ns ? address/command ?? and ? input ? hold ? time ? t ah /t ch ? 0.3 ? ? ? 0.4 ? ? ? 0.4 ? ? ? 0.5 ? ? ? 0.8 ? ? ? ns ? data \ in ? and ? data ?? mask ? to ? dk ?? hold ? time ? t dh ? 0.17 ? ? ? 0.25 ? ? ? 0.25 ? ? ? 0.3 ? ? ? 0.4 ? ? ? ns ? output ? data ? clock ?? high ? time ? t qkh ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? t ckh ? output ? data ? clock ?? low ? time ? t qkl ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? 0.9 ? 1.1 ? t ckl ? half \ clock ? period ? t qhp ? min(t qkh , ? t qkl ) ? ? ? min(t qkh , ? t qkl ) ? ? ? min(t qkh , ? t qkl ) ? ? ? min(t qkh , ? t qkl ) ? ? ? min(t qkh , ? t qkl ) ? ? ?? qk ? edge ? to ? clock ?? edge ? skew ? t ckqk ? ?0.2 ? 0.2 ? ?0.25 ? 0.25 ? ?0.25 ? 0.25 ? ?0.3 ? 0.3 ? ?0.5 ? 0.5 ? ns ? qk ? edge ? to ? output ?? data ? edge ? (7) ? t qkq0 , ?? t qkq1 ? ?0.12 ? 0.12 ? ?0.2 ? 0.2 ? ?0.2 ? 0.2 ? ?0.25 ? 0.25 ? ?0.3 ? 0.3 ? ns ? qk ? edge ? to ? any ?? output ? data ? edge ? (8) ? t qkq ? ?0.22 ? 0.22 ? ?0.3 ? 0.3 ? ?0.3 ? 0.3 ? ?0.35 ? 0.35 ? ?0.4 ? 0.4 ? ns ? qk ? edge ? to ? qvld ? t qkvld ? ?0.22 ? 0.22 ? ?0.3 ? 0.3 ? ?0.3 ? 0.3 ? ?0.35 ? 0.35 ? ?0.4 ? 0.4 ? ns ? data ? valid ? window ? t dvw ? t qhp ?\? ? ? t qhp ?\? ? ? t qhp ?\? ? ? t qhp ?\? ? ? t qhp ?\? (t qkqx ? [max] ? + ? |t qkqx ? [min]|) ? ? ?? (t qkqx ? (t qkqx ? (t qkqx ? (t qkqx ? [max] ? + ? [max] ? + ? [max] ? + ? [max] ? + |t qkqx ? |t qkqx ? |t qkqx ? |t qkqx ? [min]|) ? [min]|) ? [min]|) ? [min]|) average ? periodic ? refresh ? interval ? (9) ? t refi ? ? ? 0.24 ? ? ? 0.24 ? ? ? 0.24 ? ? ? 0.24 ? ? ? 0.24 ? s ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 10 notes: ? 1. all ? timing ? parameters ? are ? measured ? relative ? to ? the ? crossing ? point ? of ? ck/ck#, ? dk/dk# ? and ? to ? the ? crossing ? point ? with ? v ref ? of ? the ? command, ? address, ? and ? data ? signals. ? 2. outputs ? measured ? with ? equivalent ? load: ? ? 10 pf 50 ? test point dq v tt ? ? 3. tests ? for ? ac ? timing, ? idd, ? and ? electrical ? ac ? and ? dc ? characteristics ? may ? be ? conducted ? at ? nominal ? reference/supply ? voltage ? levels, ? but ? the ? related ? specifications ? and ? device ? operations ? are ? tested ? for ? the ? full ? voltage ? range ? specified. ? 4. ac ? timing ? may ? use ? a ? v il \ to \ v ih ? swing ? of ? up ? to ? 1.5v ? in ? the ? test ? environment, ? but ? input ? timing ? is ? still ? referenced ? to ? v ref ? (or ? to ? the ? crossing ? point ? for ? ck/ck#), ? and ? parameter ? specifications ? are ? tested ? for ? the ? specified ? ac ? input ? levels ? under ? normal ? use ? conditions. ? the ? minimum ? slew ? rate ? for ? the ? input ? signals ? used ? to ? test ? the ? device ? is ? 2 ? v/ns ? in ? the ? range ? between ? v il (ac) ? and ? v ih (ac). ? 5. clock ? phase ? jitter ? is ? the ? variance ? from ? clock ? rising ? edge ? to ? the ? next ? expected ? clock ? rising ? edge. ? 6. frequency ? drift ? is ? not ? allowed. ? 7. for ? a ? x36 ? device, ? dq0 \ dq17 ? is ? referenced ? to ? t qkq0 ? and ? dq18 \ dq35 ? is ? referenced ? to ? t qkq1 . ? for ? a ? x18 ? device, ? dq0 \ dq8 ? is ? referenced ? to ? t qkq0 ? and ? dq9 \ dq17 ? is ? referenced ? to ? t qkq1 . ? for ? a ? x9 ? device, ? t qkq0 ? is ? referenced ? to ? dq0 \ dq8. ? 8. t qkq ? takes ? into ? account ? the ? skew ? between ? any ? qk x ? and ? any ? q. ? 9. to ? improve ? efficiency, ? eight ? aref ? commands ? (one ? for ? each ? bank) ? can ? be ? posted ? to ? the ? memory ? on ? consecutive ? cycles ? at ? periodic ? intervals ? of ? 1.95 s. ? ? 2.8 ? clock ? input ? conditions ? differential ? input ? clock ? operating ? conditions ? parameter ? symbol ? min max ? units ? notes ? clock ? input ? voltage ? level ? v in (dc) ? \ 0.3 v ddq +0.3 ? v ? clock ? input ? differential ? voltage ? level ? v id (dc) ? 0.2 v ddq +0.6 ? v ? 8 clock ? input ? differential ? voltage ? level ? v id (ac) ? 0.4 v ddq +0.6 ? v ? 8 clock ? input ? crossing ? point ? voltage ? level ? v ix (ac) ? v ddq /2 \ 0.15 v ddq /2+0.15 ? v ? 9 ? clock ? input ? example ? ? notes: ? 1. dkx ? and ? dkx# ? have ? the ? same ? requirements ? as ? ck ? and ? ck#. ? 2. all ? voltages ? referenced ? to ? v ss . ? 3. tests ? for ? ac ? timing, ? idd ? and ? electrical ? ac ? and ? dc ? characteristics ? may ? be ? conducted ? at ? normal ? reference/supply ? voltage ? levels; ? but ? the ? related ? specifications ? and ? device ? operations ? are ? tested ? for ? the ? full ? voltage ? range ? specified. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 11 4. ac ? timing ? and ? idd ? tests ? may ? use ? a ? v il \ to \ v ih ? swing ? of ? up ? to ? 1.5v ? in ? the ? test ? environment, ? but ? input ? timing ? is ? still ? referenced ? to ? v ref ? (or ? the ? crossing ? point ? for ? ck/ck#), ? and ? parameters ? specifications ? are ? tested ? for ? the ? specified ? ac ? input ? levels ? under ? normal ? use ? conditions. ? the ? minimum ? slew ? rate ? for ? the ? input ? signals ? used ? to ? test ? the ? device ? is ? 2v/ns ? in ? the ? range ? between ? v il (ac) ? and ? v ih (ac). ? 5. the ? ac ? and ? dc ? input ? level ? specifications ? are ? as ? defined ? in ? the ? hstl ? standard ? (i.e. ? the ? receiver ? will ? effectively ? switch ? as ? a ? result ? of ? the ? signal ? crossing ? the ? ac ? input ? level, ? and ? will ? remain ? in ? that ? state ? as ? long ? as ? the ? signal ? does ? not ? ring ? back ? above[below] ? the ? dc ? input ? low[high] ? level). ? 6. the ? ck/ck# ? input ? reference ? level ? (for ? timing ? referenced ? to ? ck/ck#) ? is ? the ? point ? at ? which ? ck ? and ? ck# ? cross. ? the ? input ? reference ? level ? for ? signal ? other ? than ? ck/ck# ? is ? v ref . ? 7. ck ? and ? ck# ? input ? slew ? rate ? must ? be ?? 2v/ns ? ( ? 4v/ns ? if ? measured ? differentially). ? 8. v id ? is ? the ? magnitude ? of ? the ? difference ? between ? the ? input ? level ? on ? ck ? and ? input ? level ? on ? ck#. ? 9. the ? value ? of ? v ix ? is ? expected ? to ? equal ? v ddq /2 ? of ? the ? transmitting ? device ? and ? must ? track ? variations ? in ? the ? dc ? level ? of ? the ? same. ? 10. ck ? and ? ck# ? must ? cross ? within ? the ? region. ? 11. ck ? and ? ck# ? must ? meet ? at ? least ? v id (dc) ? (min.) ? when ? static ? and ? centered ? on ? v ddq /2. ? 12. minimum ? peak \ to \ peak ? swing. ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 12 3 ? functional ? descriptions 3.1 ? power \ up ? and ? initialization ? (1) ? the ? rldram ? ? 2 ? memory ? must ? be ? powered \ up ? and ? initialized ? using ? the ? specific ? steps ? listed ? below: ? 1. apply ? power ? by ? ramping ? up ? supply ? voltages ? v ext , ? v dd , ? v ddq , ? v ref , ? and ? v tt . ? apply ? v dd ? and ? v ext ? before ? or ? at ? the ? same ? time ? as ? v ddq ? (2) . ? power \ up ? sequence ? begins ? when ? both ? v dd ? and ? v ext ? approach ? their ? nominal ? levels. ? afterwards, ? apply ? v ddq ? before ? or ? at ? the ? same ? time ? as ? v ref ? and ? v tt . ? once ? the ? supply ? voltages ? are ? stable, ? clock ? inputs ? ck/ck# ? and ? dk/dk# ? can ? be ? applied. ? register ? nop ? commands ? to ? the ? control ? pins ? to ? avoid ? issuing ? unwanted ? commands ? to ? the ? device. ? 2. keep ? applying ? stable ? conditions ? for ? a ? minimum ? of ? 200 ? s. ? 3. register ? at ? least ? three ? consecutive ? mrs ? commands ? consisting ? of ? two ? or ? more ? dummy ? mrs ? commands ? and ? one ? valid ? mrs ? command. ? timing ? parameter ? t mrsc ? is ? not ? required ? to ? be ? met ? during ? these ? consecutive ? mrs ? commands ? but ? asserting ? a ? low ? logic ? to ? the ? address ? signals ? is ? recommended. ?? 4. t mrsc ? timing ? delay ? after ? the ? valid ? mrs ? command, ? auto ? refresh ? commands ? to ? all ? 8 ? banks ? and ? 1,024 ? nop ? commands ? must ? be ? issued ? prior ? to ? normal ? operation. ? the ? auto ? refresh ? commands ? to ? the ? 8 ? banks ? can ? be ? issued ? in ? any ? order ? with ? respect ? to ? the ? 1,024 ? nop ? commands. ? please ? note ? that ? the ? trc ? timing ? parameter ? must ? be ? met ? between ? an ? auto ? refresh ? command ? and ? a ? valid ? command ? in ? the ? same ? bank. ? 5. the ? device ? is ? now ? ready ? for ? normal ? operation. ? notes: ? 1. operational ? procedure ? other ? than ? the ? one ? listed ? above ? may ? result ? in ? undefined ? operations ? and ? may ? permanently ? damage ? the ? device. ?? 2. v ddq ? can ? be ? applied ? before ? v dd ? but ? will ? result ? in ? all ? dq ? data ? pin, ? dm, ? and ? output ? pins ? to ? go ? logic ? high ? (instead ? of ? tri \ state) ? and ? will ? remain ? high ? until ? the ? v dd ? is ? the ? same ? level ? as ? v ddq . ? this ? method ? is ? not ? recommended ? to ? avoid ? bus ? conflicts ? during ? the ? power \ up. ? ? 3.2 ? power \ up ? and ? initialization ? flowchart ? ? notes: ? 1. the ? supply ? voltages ? can ? be ? ramped ? up ? simultaneously. ? 2. the ? dummy ? and ? valid ? mrs ? commands ? must ? be ? issued ? in ? consecutive ? clock ? cycles. ? at ? least ? two ? dummy ? mrs ? commands ? are ? required. ? it ? is ? recommended ? to ? assert ? a ? low ? logic ? on ? the ? address ? signals ? during ? the ? dummy ? mrs ? commands. ? 3. the ? auto ? refresh ? commands ? can ? be ? issued ? in ? any ? order ? with ? respect ? to ? the ? 1,024 ? nop ? commands. ? however, ? timing ? parameter ? t rc ? must ? be ? met ? before ? issuing ? any ? valid ? command ? in ? a ? bank ? after ? an ? aref ? command ? to ? the ? same ? bank ? has ? been ? issued. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 13 3.3 ? power \ up ? and ? initialization ? timing ? diagram ? non \ multiplexed ? address ? mode ? notes: ? 1. it ? is ? recommended ? that ? the ? address ? input ? signals ? be ? driven ? low ? during ? the ? dummy ? mrs ? commands. ? 2. a10?a17 ? must ? be ? low. ? 3. dll ? must ? be ? reset ? if ? t ck ? or ? v dd ? are ? changed. ? 4. ck ? and ? ck# ? must ? be ? separated ? at ? all ? times ? to ? prevent ? invalid ? commands ? from ? being ? issued. ? 5. the ? auto ? refresh ? commands ? can ? be ? issued ? in ? any ? order ? with ? respect ? to ? the ? 1,024 ? nop ? commands. ? however, ? timing ? parameter ? t rc ? must ? be ? met ? before ? issuing ? any ? valid ? command ? in ? a ? bank ? after ? an ? aref ? command ? to ? the ? same ? bank ? has ? been ? issued. ? ? multiplexed ? address ? mode ? ck ck# command v ext ,v dd , v ddq , v ref ,v tt nop nop 200us(min) mrs mrs mrs ~ ~ nop ~~ aref refresh ? all ? 8 ? banks aref don t ? care ~~ t ckh t ckl t ck t mrsc address a 1,2 a 1,2 a 2,3 ay bank0 bank7 ~~ mrs ax 2,4 t mrsc ~~ any any 1024nops 6 ? notes: ? 1. it ? is ? recommended ? that ? the ? address ? input ? signals ? be ? driven ? low ? during ? the ? dummy ? mrs ? commands. ? 2. a10?a18 ? must ? be ? low. ? 3. set ? address ? a5 ? high. ? this ? enables ? the ? part ? to ? enter ? multiplexed ? address ? mode ? when ? in ? moon \ multiplexed ? mode ? operation. ? multiplexed ? address ? mode ? can ? also ? be ? entered ? at ? some ? later ? time ? by ? issuing ? an ? mrs ? command ? with ? a5 ? high. ? once ? address ? bit ? a5 ? is ? set ? high, ? tmrsc ? must ? be ? satisfied ? before ? the ? two ? cycle ? multiplexed ? mode ? mrs ? command ? is ? issued. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 14 4. address ? a5 ? must ? be ? set ? high. ? this ? and ? the ? following ? step ? set ? the ? desired ? mode ? register ? once ? the ? memory ? is ? in ? multiplexed ? address ? mode. ? 5. ck ? and ? ck# ? must ? be ? separated ? at ? all ? times ? to ? prevent ? invalid ? commands ? from ? being ? issued. ? 6. the ? auto ? refresh ? commands ? can ? be ? issued ? in ? any ? order ? with ? respect ? to ? the ? 1,024 ? nop ? commands. ? however, ? timing ? parameter ? t rc ? must ? be ? met ? before ? issuing ? any ? valid ? command ? (any) ? in ? a ? bank ? after ? an ? aref ? command ? to ? the ? same ? bank ? has ? been ? issued. ? ? 3.4 mode ? register ? setting ? and ? features ? ? ? note: ? the ? mrs ? command ? can ? only ? be ? issued ? when ? all ? banks ? are ? idle ? and ? no ? bursts ? are ? in ? progress. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 15 ? the ? mode ? register ? set ? command ? stores ? the ? data ? for ? controlling ? the ? various ? operating ? modes ? of ? the ? memory ? using ? address ? inputs ? a0 \ a17 ? as ? mode ? registers. ? during ? the ? mrs ? command, ? the ? cycle ? time ? and ? the ? read/write ? latency ? of ? the ? memory ? can ? be ? selected ? from ? different ? configurations. ? the ? mrs ? command ? also ? programs ? the ? memory ? to ? operate ? in ? either ? multiplexed ? address ? mode ? or ? non \ multiplexed ? address ? mode. ? in ? addition, ? several ? features ? can ? be ? enabled ? using ? the ? mrs ? command. ? these ? are ? the ? dll, ? drive ? impedance ? matching, ? and ? on \ die ? termination ? (odt). ? t mrsc ? must ? be ? met ? before ? any ? command ? can ? be ? issued. ? t mrsc ? is ? measured ? like ? the ? picture ? above ? in ? both ? multiplexed ? and ? non \ multiplexed ? mode. ? ? mode ? register ? diagram ? (non \ multiplexed ? address ? mode) ? a9 0 1 a8 0 1 a7 0 1 a5 0 1 a4 a3 00 01 10 11 a2 a1 a0 trc(tck) trl(tck) twl(tck) 000 445 001 445 010 667 011 889 100 334 101 556 1 1 0 n/a n/a n/a 1 1 1 n/a n/a n/a reserved n/a 5333 \ 175 reserved n/a 3533 \ 175 4 ? 3,8 200 \ 175 1 ? 3 266 \ 175 2400 \ 175 read/write ? latency ? and ? cycle ? time ? configuration 6,7 valid ? frequency ? range ? ( mhz ) configuration 1 ? 3 ? ( default ) 266 \ 175 a2 m2 config 4 8 a1 m1 reserved a0 m0 a4 m4 bl multiplexed a3 m3 burst ? length(bl) 2 ? (default) a5 m5 am address ? mux non \ multiplexed ? (default) a6 m6 na 2 dll ? enable a7 m7 dll dll ? reset dll ? reset 4 ( default ) a8 m8 im external(zq) a9 m9 odt drive ? impedance internal ? 50 ? 5 (default) a10 \ 17 m10 \ 17 0 ? 1 on address ? field mode ? register on \ die ? termination off ? (default) ? notes: ? 1. a10 \ a17 ? must ? be ? set ? to ? zero; ? a18 \ an ? are ? "don't ? cares." ?? 2. a6 ? not ? used ? in ? mrs. ? 3. bl ? = ? 8 ? is ? not ? available. ? 4. dll ? reset ? turns ? the ? dll ? off. ? 5. 30 ? % ? temperature ? variation. ? 6. t rc ? < ? 20ns ? in ? any ? configuration ? is ? only ? available ? with ?\ 25e ? and ?\ 18 ? speed ? grades. ? 7. minimum ? operating ? frequency ? for ?\ 18 ? is ? 370mhz. ? 8. the ? minimum ? trc ? is ? typically ? 3 ? cycles, ? except ? in ? the ? case ? of ? a ? write ? followed ? by ? a ? read ? to ? the ? same ? bank. ? in ? this ? instance ? the ? minimum ? t rc ? is ? 4 ? cycles. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 16 mode ? register ? diagram ? (multiplexed ? address ? mode) ? a9 0 1 a8 0 1 a7 0 1 a5 0 1 a4 a3 00 01 10 11 ay4 ay3 ax0 trc(tck) trl(tck) twl(tck) 000 456 001 456 010 678 011 8 9 10 100 345 101 567 1 1 0 n/a n/a n/a 1 1 1 n/a n/a n/a reserved n/a 5 333 \ 175 reserved n/a 2 400 \ 175 3 533 \ 175 4 ? 2,10 200 \ 175 read/write ? latency ? and ? cycle ? time ? configuration 8,9 valid ? frequency ? ran g e ? (mhz) configuration 1 ? 2 ? ( default ) 266 \ 175 1 ? 2 266 \ 175 4 8 a3 m1 reserved a4 m2 config a0 m0 multiplexed a3 m3 burst ? length(bl) 2 ? (default) a4 m4 bl dll ? enable address ? mux non \ multiplexed ? (default) m8 a8 m6 na 5 a5 m5 am a9 m7 dll dll ? reset dll ? reset 4 ( default ) im a9 m9 odt drive ? impedance internal ? 50 ? 6 ( default ) external(zq) a8 on \ die ? termination off ? (default) m10 \ 18 0 ? 1 on ax ay mode ? register a10 \ 18 a10 \ 18 ? notes: ? 1. a10 \ a18 ? must ? be ? set ? to ? zero; ? a18 \ an ? are ? "don't ? cares." ? 2. bl ? = ? 8 ? is ? not ? available. ? 3. 30 ? % ? temperature ? variation. ? 4. dll ? reset ? turns ? the ? dll ? off. ? 5. ay ? = ? 8 ? is ? not ? used ? in ? mrs. ? 6. ba0 \ ba2 ? are ? "don't ? care." ? 7. addresses ? a0, ? a3, ? a4, ? a5, ? a8, ? and ? a9 ? must ? be ? set ? as ? shown ? in ? order ? to ? activate ? the ? mode ? register ? in ? the ? multiplexed ? address ? mode. ? 8. t rc ? < ? 20ns ? in ? any ? configuration ? is ? only ? available ? with ?\ 25e ? and ?\ 18 ? speed ? grades. ? 9. minimum ? operating ? frequency ? for ?\ 18 ? is ? 370mhz. ? 10. the ? minimum ? t rc ? is ? typically ? 3 ? cycles, ? except ? in ? the ? case ? of ? a ? write ? followed ? by ? a ? read ? to ? the ? same ? bank. ? in ? this ? instance ? the ? minimum ? t rc ? is ? 4 ? cycles. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 17 3.5 ? mode ? register ? bit ? description ? configuration ? the ? cycle ? time ? and ? read/write ? latency ? can ? be ? configured ? from ? the ? different ? options ? shown ? in ? the ? mode ? register ? diagram. ? in ? order ? to ? maximize ? data ? bus ? utilization, ? the ? write ? latency ? is ? equal ? to ? read ? latency ? plus ? one. ? the ? read ? and ? write ? latencies ? are ? increased ? by ? one ? clock ? cycle ? during ? multiplexed ? address ? mode ? compared ? to ? non \ multiplexed ? mode. ? ? burst ? length ? the ? burst ? length ? of ? the ? read ? and ? write ? accesses ? to ? memory ? can ? be ? selected ? from ? three ? different ? options: ? 2, ? 4, ? and ? 8. ? changes ? in ? the ? burst ? length ? affect ? the ? width ? of ? the ? address ? bus ? and ? is ? shown ? in ? the ? burst ? length ? and ? address ? width ? table . ? the ? data ? written ? during ? a ? prior ? burst ? length ? setting ? is ? not ? guaranteed ? to ? be ? accurate ? when ? the ? burst ? length ? of ? the ? device ? is ? changed. ? burst ? length ? and ? address ? width ? table ? ? burst ? length ? 576mb ? address ? bus ? x9 ? x18 ? x36 ? 2 ? a0 \ a21 ? a0 \ a20 ? a0 \ a19 ? 4 ? a0 \ a20 ? a0 \ a19 ? a0 \ a18 ? 8 ? a0 \ a19 ? a0 \ a18 ? a0 \ a17 ? ? dll ? reset ? the ? default ? setting ? for ? this ? option ? is ? low, ? whereby ? the ? dll ? is ? disabled. ? once ? the ? mode ? register ? for ? this ? feature ? is ? set ? high, ? 1024 ? cycles ? (5 s ? at ? 200 ? mhz) ? are ? needed ? before ? a ? read ? command ? can ? be ? issued. ? this ? time ? allows ? the ? internal ? clock ? to ? be ? synchronized ? with ? the ? external ? clock. ? failing ? to ? wait ? for ? synchronization ? to ? occur ? may ? result ? in ? a ? violation ? of ? the ? t ckqk ? parameter. ? a ? reset ? of ? the ? dll ? is ? necessary ? if ? t ck ? or ? v dd ? is ? changed ? after ? the ? dll ? has ? already ? been ? enabled. ? to ? reset ? the ? dll, ? an ? mrs ? command ? must ? be ? issued ? where ? the ? dll ? reset ? mode ? register ? is ? set ? low. ? after ? waiting ? t mrsc , ? a ? subsequent ? mrs ? command ? should ? be ? issued ? whereby ? the ? dll ? reset ? mode ? register ? is ? set ? high. ? 1024 ? clock ? cycles ? are ? then ? needed ? before ? a ? read ? command ? is ? issued. ?? ? drive ? impedance ? matching ? the ? rldram ? ? 2 ? memory ? is ? equipped ? with ? programmable ? impedance ? output ? buffers. ? the ? purpose ? of ? the ? programmable ? impedance ? output ? buffers ? is ? to ? allow ? the ? user ? to ? match ? the ? driver ? impedance ? to ? the ? system. ? to ? adjust ? the ? impedance, ? an ? external ? precision ? resistor ? (rq) ? is ? connected ? between ? the ? zq ? ball ? and ? v ss . ? the ? value ? of ? the ? resistor ? must ? be ? five ? times ? the ? desired ? impedance. ? for ? example, ? a ? 300 ? resistor ? is ? required ? for ? an ? output ? impedance ? of ? 60 . ? the ? range ? of ? rq ? is ? 125?300 , ? which ? guarantees ? output ? impedance ? in ? the ? range ? of ? 25?60 ? (within ? 15 ? percent). ? output ? impedance ? updates ? may ? be ? required ? because ? over ? time ? variations ? may ? occur ? in ? supply ? voltage ? and ? temperature. ? when ? the ? external ? drive ? impedance ? is ? enabled ? in ? the ? mrs, ? the ? device ? will ? periodically ? sample ? the ? value ? of ? rq. ? an ? impedance ? update ? is ? transparent ? to ? the ? system ? and ? does ? not ? affect ? device ? operation. ? all ? data ? sheet ? timing ? and ? current ? specifications ? are ? met ? during ? an ? update. ? when ? the ? drive ? impedance ? mode ? register ? is ? set ? low ? during ? the ? mrs ? command, ? the ? memory ? provides ? an ? internal ? impedance ? at ? the ? output ? buffer ? of ? 50 ? (30% ? with ? temperature ? variation). ? this ? impedance ? is ? also ? periodically ? sampled ? and ? adjusted ? to ? compensate ? for ? variation ? in ? supply ? voltage ? and ? temperature. ? ? address ? multiplexing ?? although ? the ? rldram ? ? 2 ? memory ? is ? capable ? of ? accepting ? all ? the ? addresses ? in ? a ? single ? rising ? clock ? edge, ? this ? memory ? can ? be ? programmed ? to ? operate ? in ? multiplexed ? address ? mode, ? which ? is ? very ? similar ? to ? a ? traditional ? dram. ? in ? multiplexed ? address ? mode, ? the ? address ? can ? be ? sent ? to ? the ? memory ? in ? two ? parts ? within ? two ? consecutive ? rising ? clock ? edges. ? this ? minimizes ? the ? number ? of ? address ? signal ? connections ? between ? the ? controller ? and ? the ? memory ? by ? reducing ? the ? address ? bus ? to ? a ? maximum ? of ? only ? 11 ? lines. ? since ? the ? memory ? requires ? two ? clock ? cycles ? to ? read ? and ? write ? the ? data, ? data ? bus ? efficiency ? is ? affected ? when ? operating ? in ? continuous ? burst ? mode ? with ? a ? burst ? length ? of ? 2 ? setting. ? bank ? addresses ? are ? provided ? to ? the ? memory ? at ? the ? same ? time ? as ? the ? write ? and ? read ? commands ? together ? with ? the ? first ? address ? part, ? ax. ? the ? second ? address ? part, ? ay, ? is ? then ? issued ? to ? the ? memory ? on ? the ? next ? rising ? clock ? edge. ? aref ? commands ? only ? require ? the ? bank ? address. ? since ? aref ? commands ? do ? not ? need ? a ? second ? consecutive ? clock ? for ? address ? latching, ? they ? may ? be ? issued ? on ? consecutive ? clocks. ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 18 address ? mapping ? in ? multiplexed ? address ? mode ? data ? width ? burst ? length ? address ? ball ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? x36 ? 2 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? ay ? x ? a1 ? a2 ? x ? a6 ? a7 ? a19 ? a11 ? a12 ? a16 ? a15 ? 4 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? ay ? x ? a1 ? a2 ? x ? a6 ? a7 ? x ? a11 ? a12 ? a16 ? a15 ? 8 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? x ? ay ? x ? a1 ? a2 ? x ? a6 ? a7 ? x ? a11 ? a12 ? a16 ? a15 ? x18 ? 2 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? ay ? a20 ? a1 ? a2 ? x ? a6 ? a7 ? a19 ? a11 ? a12 ? a16 ? a15 ? 4 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? ay ? x ? a1 ? a2 ? x ? a6 ? a7 ? a19 ? a11 ? a12 ? a16 ? a15 ? 8 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? ay ? x ? a1 ? a2 ? x ? a6 ? a7 ? x ? a11 ? a12 ? a16 ? a15 ? x9 ? 2 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? ay ? a20 ? a1 ? a2 ? a21 ? a6 ? a7 ? a19 ? a11 ? a12 ? a16 ? a15 ? 4 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? ay ? a20 ? a1 ? a2 ? x ? a6 ? a7 ? a19 ? a11 ? a12 ? a16 ? a15 ? 8 ? ax ? a0 ? a3 ? a4 ? a5 ? a8 ? a9 ? a10 ? a13 ? a14 ? a17 ? a18 ? ay ? x ? a1 ? a2 ? x ? a6 ? a7 ? a19 ? a11 ? a12 ? a16 ? a15 ? note: ? x ? = ? don?t ? care. ? on \ die ? termination ? (odt) ? if ? the ? odt ? is ? enabled, ? the ? dqs ? and ? dm ? are ? terminated ? to ? v tt ? with ? a ? resistance ? r tt . ? the ? command, ? address, ? qvld, ? and ? clock ? signals ? are ? not ? terminated. ? figure ? 3.1 ? shows ? the ? equivalent ? circuit ? of ? a ? dq ? receiver ? with ? odt. ? the ? odt ? function ? is ? dynamically ? switched ? off ? when ? a ? dq ? begins ? to ? drive ? after ? a ? read ? command ? is ? issued. ? similarly, ? odt ? is ? designed ? to ? switch ? on ? at ? the ? dqs ? after ? the ? memory ? has ? issued ? the ? last ? piece ? of ? data. ? the ? dm ? pin ? will ? always ? be ? terminated. ? odt ? dc ? parameters ? table ? description ? symbol ? min max units ? notes termination ? voltage ? v tt ? 0.95 ? x ? v ref ? 1.05 ? x ? v ref ? v ? 1, ? 2 ? on \ die ? termination ? r tt ? 125 185 ? 3 notes: ? 1. all ? voltages ? referenced ? to ? v ss ? (gnd). ? 2. v tt ? is ? expected ? to ? be ? set ? equal ? to ? v ref ? and ? must ? track ? variations ? in ? the ? dc ? level ? of ? v ref . ? 3. the ? r tt ? value ? is ? measured ? at ? 95c ? t c . ? ? figure ? 3.1 ? odt ? equivalent ? circuit ??
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 19 3.6 ? deselect/no ? operation ? (desl/nop) ? the ? deselect ? command ? is ? used ? to ? prevent ? unwanted ? operations ? from ? being ? performed ? in ? the ? memory ? device ? during ? wait ? or ? idle ? states. ? operations ? already ? registered ? to ? the ? memory ? prior ? to ? the ? assertion ? of ? the ? deselect ? command ? will ? not ? be ? cancelled. ? ? 3.7 ? read ? operation ? (read) ? the ? read ? command ? performs ? burst \ oriented ? data ? read ? accesses ? in ? a ? bank ? of ? the ? memory ? device. ? the ? read ? command ? is ? initiated ? by ? registering ? the ? we# ? and ? ref# ? signals ? logic ? high ? while ? the ? cs# ? is ? in ? logic ? low ? state. ? in ? non \ multiplexed ? address ? mode, ? both ? an ? address ? and ? a ? bank ? address ? must ? be ? provided ? to ? the ? memory ? during ? the ? assertion ? of ? the ? read ? command. ? in ? multiplexed ? mode, ? the ? bank ? address ? and ? the ? first ? part ? of ? the ? address, ? ax, ? must ? be ? supplied ? together ? with ? the ? read ? command. ? the ? second ? part ? of ? the ? address, ? ay, ? must ? be ? latched ? to ? the ? memory ? on ? the ? subsequent ? rising ? edge ? of ? the ? ck ? clock. ? data ? being ? accessed ? will ? be ? available ? in ? the ? data ? bus ? a ? certain ? amount ? of ? clock ? cycles ? later ? depending ? on ? the ? read ? latency ? configuration ? setting. ? ? data ? driven ? in ? the ? dq ? signals ? are ? edge \ aligned ? to ? the ? free \ running ? output ? data ? clocks ? qkx ? and ? qkx#. ? a ? half ? clock ? cycle ? before ? the ? read ? data ? is ? available ? on ? the ? data ? bus, ? the ? data ? valid ? signal, ? qvld, ? will ? transition ? from ? logic ? low ? to ? high. ? the ? qvld ? signal ? is ? also ? edge \ aligned ? to ? the ? data ? clock ? qkx ? and ? qkx#. ? ? if ? no ? other ? commands ? have ? been ? registered ? to ? the ? device ? when ? the ? burst ? read ? operation ? is ? finished, ? the ? dq ? signals ? will ? go ? to ? high \ z ? state. ? the ? qvld ? signal ? transition ? from ? logic ? high ? to ? logic ? low ? on ? the ? last ? bit ? of ? the ? read ? burst. ? please ? note ? that ? if ? ck/ck# ? violates ? the ? vid ? (dc) ? specification ? while ? a ? read ? burst ? is ? occurring, ? qvld ? will ? remain ? high ? until ? a ? dummy ? read ? command ? is ? registered. ? the ? qk ? clocks ? are ? free \ running ? and ? will ? continue ? to ? cycle ? after ? the ? read ? burst ? is ? complete. ? back \ to \ back ? read ? commands ? are ? permitted ? which ? allows ? for ? a ? continuous ? flow ? of ? output ? data. ? ? a non \ multiplexed ? mode ck# ck cs# we# ref# address ba* bank address don?t ? care ax multiplexed ? mode ck# ck cs# we# ref# address ba* bank address ay ? read ? command ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 20 ? basic ? read ? burst ? with ? qvld: ? bl=2 ? & ? rl=4 ? notes: ? 1. minimum ? read ? data ? valid ? window ? can ? be ? expressed ? as ? min(t qkh , ? t qkl ) ? ? ? 2 ? x ? max(t qkqx ). ? 2. t ckh ? and ? t ckl ? are ? recommended ? to ? have ? 50% ? / ? 50% ? duty. ? 3. t qkq0 ? is ? referenced ? to ? dq0?dq17 ? in ? x36 ? and ? dq0?dq8 ? in ? x18. ? t qkq1 ? is ? referenced ? to ? dq18?dq35 ? in ? x36 ? and ? dq9?dq17 ? in ? x18. ? 4. t qkq ? takes ? into ? account ? the ? skew ? between ? any ? qkx ? and ? any ? dq. ? 5. t ckqk ? is ? specified ? as ? ck ? rising ? edge ? to ? qk ? rising ? edge. ? ? 3.8 ? write ? operation ? (write) ? the ? write ? command ? performs ? burst \ oriented ? data ? write ? accesses ? in ? a ? bank ? of ? the ? memory ? device. ?? the ? write ? command ? is ? initiated ? by ? registering ? the ? ref# ? signal ? logic ? high ? while ? the ? cs# ? and ? we# ? signals ? are ? in ? logic ? low ? state. ? in ? non \ multiplexed ? address ? mode, ? both ? an ? address ? and ? a ? bank ? address ? must ? be ? provided ? to ? the ? memory ? during ? the ? assertion ? of ? the ? write ? command. ? in ? multiplexed ? mode, ? the ? bank ? address ? and ? the ? first ? part ? of ? the ? address, ? ax, ? must ? be ? supplied ? together ? with ? the ? write ? command. ? the ? second ? part ? of ? the ? address, ? ay, ? must ? be ? latched ? to ? the ? memory ? on ? the ? subsequent ? rising ? edge ? of ? the ? ck ? clock. ? input ? data ? to ? be ? written ? to ? the ? device ? can ? be ? registered ? several ? clock ? cycles ? later ? depending ? on ? the ? write ? latency ? configuration ? setting. ? the ? write ? latency ? is ? always ? one ? cycle ? longer ? than ? the ? programmed ? read ? latency. ? the ? dm ? signal ? can ? mask ? the ? input ? data ? by ? setting ? this ? signal ? logic ? high. ? ? at ? least ? one ? nop ? command ? in ? between ? a ? read ? and ? write ? commands ? is ? required ? in ? order ? to ? avoid ? data ? bus ? contention. ? the ? setup ? and ? hold ? times ? for ? dm ? and ? data ? signals ? are ? t ds ? and ? t dh , ? which ? are ? referenced ? to ? the ? dk ? clocks. ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 21 a non \ multiplexed ? mode ck# ck cs# we# ref# address ba* bank address don?t ? care ax multiplexed ? mode ck# ck cs# we# ref# address ba* bank address ay write ? command ? basic ? write ? burst ? with ? dm ? timing: ? bl=4 ? & ? wl=5 ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 22 write ? followed ? by ? read: ? bl=2 ? rl=4 ? & ? wl=5 ? 3.9 ? auto ? refresh ? command ? (aref) ? the ? auto ? refresh ? command ? performs ? a ? refresh ? cycle ? on ? one ? row ? of ? a ? specific ? bank ? of ? the ? memory. ? only ? bank ? addresses ? are ? required ? together ? with ? the ? control ? the ? pins. ? therefore, ? auto ? refresh ? commands ? can ? be ? issued ? on ? subsequent ? ck ? clock ? cycles ? on ? both ? multiplexed ? and ? non \ multiplexed ? address ? mode. ? any ? command ? following ? an ? auto ? refresh ? command ? must ? meet ? a ? trc ? timing ? delay ? or ? later. ?? ? 01 23 456 arefx bax bay arefy nop nop nop anycomx anycomy command bank ? address don?t ? care ck ck# qkx qkx# t ckh t ckl t ck bax bay t rc t rc aref ? example ? in ? t rc (t ck )=5 ? option: ? configuration=5 ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 23 auto ? refresh ? command ? 3.10 ? command ? truth ? table ? operation ? code ? cs# ? we# ? ref# ? ax ? bax ? device ? deselect/no ? operation ? desl/nop ? h ? x ? x ? x ? x ? mode ? register ? set ? mrs ? l ? l ? l ? opcode ? x ? read ? read ? l ? h ? h ? a ? ba ? write ? write ? l ? l ? h ? a ? ba ? auto ? refresh ? aref ? l ? h ? l ? x ? ba ? notes: ? 1. x ? = ? "don't ? care;" ? h ? = ? logic ? high; ? l ? = ? logic ? low; ? a ? = ? valid ? address; ? ba ? = ? valid ? bank ? address. ? 2. during ? mrs, ? only ? address ? inputs ? a0 \ a17 ? are ? used. ? 3. address ? width ? changes ? with ? burst ? length. ? 4. all ? input ? states ? or ? sequences ? not ? shown ? are ? illegal ? or ? reserved. ? 5. all ? command ? and ? address ? inputs ? must ? meet ? setup ? and ? hold ? times ? around ? the ? rising ? edge ? of ? ck. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 24 3.11 ? on \ die ? termination ? (odt) ? timing ? examples. ? 0123456 rd ba2, ? a2 nop nop nop nop nop nop command address don?t ? care undefined q2 \ 0 qvld dq read ? latency ? = ? 4 ck ck# qkx qkx# dq ? odt ? on dq ? odt nop dq ? odt ? off dq ? odt ? on 7 q2 \ 1 q2 \ 2 q2 \ 3 t qkvld t qkvld read ? operation ? with ? odt: ? rl=4 ? & ? bl=4 read ? to ? write ? with ? odt: ? rl=4 ? & ? bl=2 ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 25 4 ? ieee ? 1149.1 ? tap ? and ? boundary ? scan ? rldram ? ? 2 ? memory ? devices ? have ? a ? serial ? boundary \ scan ? test ? access ? port ? (tap) ? that ? allow ? the ? use ? of ? a ? limited ? set ? of ? jtag ? instructions ? to ? test ? the ? interconnection ? between ? the ? memory ? i/os ? and ? printed ? circuit ? board ? traces ? or ? other ? components. ? in ? conformance ? with ? ieee ? standard ? 1149.1, ? the ? memory ? contains ? a ? tap ? controller, ? instruction ? register, ? boundary ? scan ? register, ? bypass ? register, ? and ? id ? register. ? the ? tap ? operates ? in ? accordance ? with ? ieee ? standard ? 1149.1 \ 2001 ? (jtag) ? with ? the ? exception ? of ? the ? zq ? pin. ? to ? guarantee ? proper ? boundary \ scan ? testing ? of ? the ? zq ? pin, ? mrs ? bit ? m8 ? needs ? to ? be ? set ? to ? 0 ? until ? the ? jtag ? testing ? of ? the ? pin ? is ? complete. ? note ? that ? on ? power ? up, ? the ? default ? state ? of ? mrs ? bit ? m8 ? is ? logic ? low. ? ? if ? the ? memory ? boundary ? scan ? register ? is ? to ? be ? used ? upon ? power ? up ? and ? prior ? to ? the ? initialization ? of ? the ? device, ? the ? ck ? and ? ck# ? pins ? meet ? v id (dc) ? or ? cs# ? be ? held ? high ? from ? power ? up ? until ? testing. ? not ? doing ? so ? could ? result ? in ? inadvertent ? mrs ? commands ? to ? be ? loaded, ? and ? subsequently ? cause ? unexpected ? results ? from ? address ? pins ? that ? are ? dependent ? upon ? the ? state ? of ? the ? mode ? register. ? if ? these ? measures ? cannot ? be ? taken, ? the ? part ? must ? be ? initialized ? prior ? to ? boundary ? scan ? testing. ? if ? a ? full ? initialization ? is ? not ? practical ? or ? feasible ? prior ? to ? boundary ? scan ? testing, ? a ? single ? mrs ? command ? with ? desired ? settings ? may ? be ? issued ? instead. ? after ? the ? single ? mrs ? command ? is ? issued, ? the ? t mrsc ? parameter ? must ? be ? satisfied ? prior ? to ? boundary ? scan ? testing. ? ? 4.1 ? disabling ? the ? jtag ? feature ? the ? rldram ? ? 2 ? memory ? can ? operate ? without ? using ? the ? jtag ? feature. ? to ? disable ? the ? tap ? controller, ? tck ? must ? be ? tied ? low ? (v ss ) ? to ? prevent ? clocking ? of ? the ? device. ? tdi ? and ? tms ? are ? internally ? pulled ? up ? and ? may ? be ? left ? disconnected. ? they ? may ? alternately ? be ? connected ? to ? v dd ? through ? a ? pull \ up ? resistor. ? tdo ? should ? be ? left ? disconnected. ? on ? power \ up, ? the ? device ? will ? come ? up ? in ? a ? reset ? state, ? which ? will ? not ? interfere ? with ? device ? operation. ? ? 4.2 ? test ? access ? port ? signal ? list: ? test ? clock ? (tck) ? this ? signal ? uses ? v dd ? as ? a ? power ? supply. ? the ? test ? clock ? is ? used ? only ? with ? the ? tap ? controller. ? all ? inputs ? are ? captured ? on ? the ? rising ? edge ? of ? tck. ? all ? outputs ? are ? driven ? from ? the ? falling ? edge ? of ? tck. ? ? test ? mode ? select ? (tms) ? this ? signal ? uses ? v dd ? as ? a ? power ? supply. ? the ? tms ? input ? is ? used ? to ? send ? commands ? to ? the ? tap ? controller ? and ? is ? sampled ? on ? the ? rising ? edge ? of ? tck. ? ? test ? data \ in ? (tdi) ? this ? signal ? uses ? v dd ? as ? a ? power ? supply. ? the ? tdi ? input ? is ? used ? to ? serially ? input ? test ? instructions ? and ? information ? into ? the ? registers ? and ? can ? be ? connected ? to ? the ? input ? of ? any ? of ? the ? registers. ? the ? register ? between ? tdi ? and ? tdo ? is ? chosen ? by ? the ? instruction ? that ? is ? loaded ? into ? the ? tap ? instruction ? register. ? tdi ? is ? connected ? to ? the ? most ? significant ? bit ? (msb) ? of ? any ? register. ? for ? more ? information ? regarding ? instruction ? register ? loading, ? please ? see ? the ? tap ? controller ? state ? diagram. ? ? test ? data \ out ? (tdo) ? this ? signal ? uses ? v ddq ? as ? a ? power ? supply. ? the ? tdo ? output ? ball ? is ? used ? to ? serially ? clock ? test ? instructions ? and ? data ? out ? from ? the ? registers. ? the ? tdo ? output ? driver ? is ? only ? active ? during ? the ? shift \ ir ? and ? shift \ dr ? tap ? controller ? states. ? in ? all ? other ? states, ? the ? tdo ? pin ? is ? in ? a ? high \ z ? state. ? the ? output ? changes ? on ? the ? falling ? edge ? of ? tck. ? tdo ? is ? connected ? to ? the ? least ? significant ? bit ? (lsb) ? of ? any ? register. ? for ? more ? information, ? please ? see ? the ? tap ? controller ? state ? diagram. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 26 4.3 ? tap ? controller ? state ? and ? block ? diagram ? ? ? note1 bypass ? register ? (1 ? bit) identification ? register ? (32 ? bits) instruction ? register ? (8 bits) tap ? controller tdo tms tck tdi control ? signals ? note: ? 113 ? boundary ? scan ? registers ? in ? rldram ? ? 2 ? memory ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 27 4.4 ? performing ? a ? tap ? reset ? a ? reset ? is ? performed ? by ? forcing ? tms ? high ? (v dd ) ? for ? five ? rising ? edges ? of ? tck. ? reset ? may ? be ? performed ? while ? the ? sram ? is ? operating ? and ? does ? not ? affect ? its ? operation. ? at ? power \ up, ? the ? tap ? is ? internally ? reset ? to ? ensure ? that ? tdo ? comes ? up ? in ? a ? high \ z ? state. ? ? 4.5 ? tap ? registers ? registers ? are ? connected ? between ? the ? tdi ? and ? tdo ? pins ? and ? allow ? data ? to ? be ? scanned ? into ? and ? out ? of ? the ? sram ? test ? circuitry . ? only ? one ? register ? can ? be ? selected ? at ? a ? time ? through ? the ? instruction ? registers. ? data ? is ? serially ? loaded ? into ? the ? tdi ? pin ? on ? the ? rising ? edge ? of ? tck ? and ? output ? on ? the ? tdo ? pin ? on ? the ? falling ? edge ? of ? tck. ? ? instruction ? register ? this ? register ? is ? loaded ? during ? the ? update \ ir ? state ? of ? the ? tap ? controller. ? at ? power \ up, ? the ? instruction ? register ? is ? loaded ? with ? the ? idcode ? instruction. ? it ? is ? also ? loaded ? with ? the ? idcode ? instruction ? if ? the ? controller ? is ? placed ? in ? a ? reset ? state ? as ? described ? in ? the ? previous ? section. ? when ? the ? tap ? controller ? is ? in ? the ? capture \ ir ? state, ? the ? two ? lsbs ? are ? loaded ? with ? a ? binary ? ?01? ? pattern ? to ? allow ? for ? fault ? isolation ? of ? the ? board \ level ? serial ? test ? data ? path. ? ? bypass ? register ? the ? bypass ? register ? is ? a ? single \ bit ? register ? that ? can ? be ? placed ? between ? the ? tdi ? and ? tdo ? balls. ? this ? allows ? data ? to ? be ? shifted ? through ? the ? memory ? device ? with ? minimal ? delay. ? the ? bypass ? register ? is ? set ? low ? (v ss ) ? when ? the ? bypass ? instruction ? is ? executed. ? ? boundary ? scan ? register ? the ? boundary ? scan ? register ? is ? connected ? to ? all ? the ? input ? and ? bidirectional ? balls ? on ? the ? device. ? several ? balls ? are ? also ? included ? in ? the ? scan ? register ? to ? reserved ? balls. ? the ? boundary ? scan ? register ? is ? loaded ? with ? the ? contents ? of ? the ? memory ? input ? and ? output ? ring ? when ? the ? tap ? controller ? is ? in ? the ? capture \ dr ? state ? and ? is ? then ? placed ? between ? the ? tdi ? and ? tdo ? balls ? when ? the ? controller ? is ? moved ? to ? the ? shift \ dr ? state. ? each ? bit ? corresponds ? to ? one ? of ? the ? balls ? on ? the ? device ? package. ? the ? msb ? of ? the ? register ? is ? connected ? to ? tdi, ? and ? the ? lsb ? is ? connected ? to ? tdo. ? ? identification ? (id) ? register ? the ? id ? register ? is ? loaded ? with ? a ? vendor \ specific, ? 32 \ bit ? code ? during ? the ? capture \ dr ? state ? when ? the ? idcode ? command ? is ? loaded ? in ? the ? instruction ? register. ? the ? idcode ? is ? hardwired ? into ? the ? device ? and ? can ? be ? shifted ? out ? when ? the ? tap ? controller ? is ? in ? the ? shift \ dr ? state. ? ? 4.6 ? scan ? register ? sizes ? ? register ? name ? bit ? size ? instruction ? register ? 8 ? bypass ? register ? 1 ? boundary ? scan ? register ? 113 ? identification ? (id) ? register ? 32 ? ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 28 4.7 ? tap ? instruction ? set ? many ? instructions ? are ? possible ? with ? an ? eight \ bit ? instruction ? register ? and ? all ? valid ? combinations ? are ? listed ? in ? the ? tap ? instruction ? code ? table. ? all ? other ? instruction ? codes ? that ? are ? not ? listed ? on ? this ? table ? are ? reserved ? and ? should ? not ? be ? used. ? instructions ? are ? loaded ? into ? the ? tap ? controller ? during ? the ? shift \ ir ? state ? when ? the ? instruction ? register ? is ? placed ? between ? tdi ? and ? tdo. ? during ? this ? state, ? instructions ? are ? shifted ? from ? the ? instruction ? register ? through ? the ? tdi ? and ? tdo ? pins. ? to ? execute ? an ? instruction ? once ? it ? is ? shifted ? in, ? the ? tap ? controller ? must ? be ? moved ? into ? the ? update \ ir ? state. ? ? extest ? the ? extest ? instruction ? allows ? circuitry ? external ? to ? the ? component ? package ? to ? be ? tested. ? boundary \ scan ? register ? cells ? at ? output ? balls ? are ? used ? to ? apply ? a ? test ? vector, ? while ? those ? at ? input ? balls ? capture ? test ? results. ? typically, ? the ? first ? test ? vector ? to ? be ? applied ? using ? the ? extest ? instruction ? will ? be ? shifted ? into ? the ? boundary ? scan ? register ? using ? the ? preload ? instruction. ? thus, ? during ? the ? update \ ir ? state ? of ? extest, ? the ? output ? driver ? is ? turned ? on, ? and ? the ? preload ? data ? is ? driven ? onto ? the ? output ? balls. ? ? idcode ? the ? idcode ? instruction ? causes ? a ? vendor \ specific, ? 32 \ bit ? code ? to ? be ? loaded ? into ? the ? identification ? register. ? it ? also ? places ? the ? identification ? register ? between ? the ? tdi ? and ? tdo ? balls ? and ? allows ? the ? idcode ? to ? be ? shifted ? out ? of ? the ? device ? when ? the ? tap ? controller ? enters ? the ? shift \ dr ? state. ? the ? idcode ? instruction ? is ? loaded ? into ? the ? instruction ? register ? upon ? power \ up ? or ? whenever ? the ? tap ? controller ? is ? given ? a ? test ? logic ? reset ? state. ? ? high \ z ? the ? high \ z ? instruction ? causes ? the ? bypass ? register ? to ? be ? connected ? between ? the ? tdi ? and ? tdo. ? this ? places ? all ? rldram ? ? 2 ? memory ? outputs ? into ? a ? high \ z ? state. ? ? clamp ? when ? the ? clamp ? instruction ? is ? loaded ? into ? the ? instruction ? register, ? the ? data ? driven ? by ? the ? output ? balls ? are ? determined ? from ? the ? values ? held ? in ? the ? boundary ? scan ? register. ? ? sample/preload ? when ? the ? sample/preload ? instruction ? is ? loaded ? into ? the ? instruction ? register ? and ? the ? tap ? controller ? is ? in ? the ? capture \ dr ? state, ? a ? snapshot ? of ? data ? on ? the ? inputs ? and ? bidirectional ? balls ? is ? captured ? in ? the ? boundary ? scan ? register. ? the ? user ? must ? be ? aware ? that ? the ? tap ? controller ? clock ? can ? only ? operate ? at ? a ? frequency ? up ? to ? 50 ? mhz, ? while ? the ? memory ? clock ? operates ? significantly ? faster. ? because ? there ? is ? a ? large ? difference ? between ? the ? clock ? frequencies, ? it ? is ? possible ? that ? during ? the ? capture \ dr ? state, ? an ? input ? or ? output ? will ? undergo ? a ? transition. ? the ? tap ? may ? then ? try ? to ? capture ? a ? signal ? while ? in ? transition ? (metastable ? state). ? this ? will ? not ? harm ? the ? device, ? but ? there ? is ? no ? guarantee ? as ? to ? the ? value ? that ? will ? be ? captured. ? repeatable ? results ? may ? not ? be ? possible. ? to ? ensure ? that ? the ? boundary ? scan ? register ? will ? capture ? the ? correct ? value ? of ? a ? signal, ? the ? memory ? signal ? must ? be ? stabilized ? long ? enough ? to ? meet ? the ? tap ? controller?s ? capture ? setup ? plus ? hold ? time ? (t cs ? plus ? t ch ). ? the ? memory ? clock ? input ? might ? not ? be ? captured ? correctly ? if ? there ? is ? no ? way ? in ? a ? design ? to ? stop ? (or ? slow) ? the ? clock ? during ? a ? sample/ ? preload ? instruction. ? if ? this ? is ? an ? issue, ? it ? is ? still ? possible ? to ? capture ? all ? other ? signals ? and ? simply ? ignore ? the ? value ? of ? the ? ck ? and ? ck# ? captured ? in ? the ? boundary ? scan ? register. ? once ? the ? data ? is ? captured, ? it ? is ? possible ? to ? shift ? out ? the ? data ? by ? putting ? the ? tap ? into ? the ? shift \ dr ? state. ? this ? places ? the ? boundary ? scan ? register ? between ? the ? tdi ? and ? tdo ? balls. ? ? bypass ? when ? the ? bypass ? instruction ? is ? loaded ? in ? the ? instruction ? register ? and ? the ? tap ? is ? placed ? in ? a ? shift \ dr ? state, ? the ? bypass ? register ? is ? placed ? between ? tdi ? and ? tdo. ? the ? advantage ? of ? the ? bypass ? instruction ? is ? that ? it ? shortens ? the ? boundary ? scan ? path ? when ? multiple ? devices ? are ? connected ? together ? on ? a ? board. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 29 4.8 ? tap ? dc ? electrical ? characteristics ? and ? operating ? conditions ? (+0c ?? t c ?? +95c; ? +1.7v ?? v dd ?? +1.9v, ? unless ? otherwise ? noted) ? description ? conditions ? symbol ? min ? max ? units ? notes ? input ? high ? (logic ? 1) ? voltage ? ? v ih ? v ref ? + ? 0.15 ? v ddq ? + ? 0.3 ? v ? 1, ? 2 ? input ? low ? (logic ? 0) ? voltage ? ? v il ? v ssq ? ? ? 0.3 ? v ref ? ? ? 0.15 ? v ? 1, ? 2 ? input ? leakage ? current ? 0v ?? v in ?? v dd ? i li ? ? ? 5.0 ? 5.0 ? a ?? output ? leakage ? current ? output ? disabled, ? 0v ?? v in ?? v ddq ? i lo ? ? ? 5.0 ? 5.0 ? a ?? output ? low ? voltage ? i olc ? =100 ? a ? v ol1 ?\? 0.2 ? v ? 1 ? output ? low ? voltage ? i olt ? = ? 2ma ? v ol2 ?\? 0.4 ? v ? 1 ? output ? high ? voltage ? |i ohc | ? =100 ? a ? v oh1 ? v ddq ?\? 0.2 ?\? v ? 1 ? output ? high ? voltage ? |i oht ? | ? = ? 2ma ? v oh2 ? v ddq ?\? 0.4 ?\? v ? 1 ? notes: ? 1. all ? voltages ? referenced ? to ? vss ? (gnd). ? 2. overshoot ? = ? v ih (ac) ?? v dd ? + ? 0.7v ? for ? t ? ? t ck /2; ? undershoot ? = ? v il (ac) ?? ?0.5v ? for ? t ? ? t ck /2; ? during ? normal ? operation, ? v ddq ? must ? not ? exceed ? v dd . ? ? 4.9 ? tap ? ac ? electrical ? characteristics ? and ? operating ? conditions ? (+0c ?? t c ?? +95c; ? +1.7v ?? v dd ?? +1.9v) ? description ? symbol ? min ? max ? units ? clock ? clock ? cycle ? time ? t thth ? 20 ?? ns ? clock ? frequency ? f tf ? ? 50 ? mhz ? clock ? high ? time ? t thtl ? 10 ?? ns ? clock ? low ? time ? t tlth ? 10 ?? ns ? tdi/tdo ? times ? tck ? low ? to ? tdo ? unknown ? t tlox ? 0 ?? ns ? tck ? low ? to ? tdo ? valid ? t tlov ? ? 10 ? ns ? tdi ? valid ? to ? tck ? high ? t dvth ? 5 ?? ns ? tck ? high ? to ? tdi ? invalid ? t thdx ? 5 ?? ns ? setup ? times ? tms ? setup ? t mvth ? 5 ?? ns ? capture ? setup ? t cs ? 5 ?? ns ? hold ? times ? tms ? hold ? t tmhx ? 5 ?? ns ? capture ? hold ? t ch ? 5 ?? ns ? note: ? t cs ? and ? t ch ? refer ? to ? the ? setup ? and ? hold ? time ? requirements ? of ? latching ? data ? from ? the ? boundary ? scan ? register. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 30 4.10 ? tap ? timing ? ? 4.11 ? tap ? instruction ? codes ? instruction ? code ? description extest ? 0000 ? 0000 ? captures ? input ? and ? output ? ring ? contents. ? places ? the ? boundary ? scan ? register ? between ? tdi ? and ? tdo. ? this ? operation ? does ? not ? affect ? device ? operations ? idcode ? 0010 ? 0001 ? loads ? the ? id ? register ? with ? the ? vendor ? id ? code ? and ? places ? the ? register ? between ? tdi ? and ? tdo; ? this ? operation ? does ? not ? affect ? device ? operations ? sample/preload ? 0000 ? 0101 ? captures ? i/o ? ring ? contents; ? places ? the ? boundary ? scan ? register ? between ? tdi ? and ? tdo clamp ? 0000 ? 0111 ? selects ? the ? bypass ? register ? to ? be ? connected ? between ? tdi ? and ? tdo; ? data ? driven ? by ? output ? balls ? are ? determined ? from ? values ? held ? in ? the ? boundary ? scan ? register ? high \ z ? 0000 ? 0011 ? selects ? the ? bypass ? register ? to ? be ? connected ? between ? tdi ? and ? tdo; ? all ? outputs ? are ? forced ? into ? high \ z ? bypass ? 1111 ? 1111 ? places ? the ? bypass ? register ? between ? tdi ? and ? tdo; ? this ? operation ? does ? not ? affect ? device operations ? note: ? all ? other ? remaining ? instruction ? codes ? not ? mentioned ? in ? the ? above ? table ? are ? reserved ? and ? should ? not ? be ? used. ?? ? 4.12 ? identification ? (id) ? register ? definition ? instruction ? field ? all ? devices description ? revision ? number ? (31:28) ? abcd ? ab ? = ? die ? revision cd ? = ? 00 ? for ? x9, ? 01 ? for ? x18, ? 10 ? for ? x36 ? device ? id ? (27:12) ? 00jkidef10100111 ? def ? = ? 000 ? for ? 288mb, ? 001 ? for ? 576mb i ? = ? 0 ? for ? common ? i/o, ? 1 ? for ? separate ? i/o ? jk ? = ? 01 ? for ? rldram ? ? 2 ?? memory ? vendor ? id ? code ? (11:1) ? 000 ? 1101 ? 0101 allows ? unique ? identification ? of ? vendor id ? register ? presence ? indicator ? (0) ? 1 ? indicates ? the ? presence ? of ? an ? id ? register ? 4.13 ? tap ? input ? ac ? logic ? levels ? (+0c ?? t c ?? +95c; ? +1.7v ?? v dd ?? +1.9v, ? unless ? otherwise ? noted) ? description ? symbol ? min ? max ? units ? input ? high ? (logic ? 1) ? voltage ? v ih ? v ref ? + ? 0.3 ?\? v ? input ? low ? (logic ? 0) ? voltage ? v il ?\? v ref ?\? 0.3 ? v ? note: ? all ? voltages ? referenced ? to ? v ss ? (gnd).
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 31 4.14 ? boundary ? scan ? order ? signal ? name bump signal ? name bump signal ? name bump x9 x18 x36 id x9 x18 x36 id x9 x18 x36 id 1 dk dk dk1 k1 39 dnu dnu dq30 r11 77 dnu dnu dq2 c11 2 dk# dk# dk1# k2 40 dnu dnu dq30 r11 78 dnu dnu dq2 c11 3 cs# cs# cs# l2 41 dnu dnu dq32 p11 79 dq1 dq1 dq3 c10 4 ref# ref# ref# l1 42 dnu dnu dq32 p11 80 dq1 dq1 dq3 c10 5 we# we# we# m1 43 dq5 dq10 dq33 p10 81 dnu dnu dq0 b11 6 a17 a17 a17 m3 44 dq5 dq10 dq33 p10 82 dnu dnu dq0 b11 7 a16 a16 a16 m2 45 dnu dnu dq34 n11 83 dq0 dq0 dq1 b10 8 a18 a18 a18 n1 46 dnu dnu dq34 n11 84 dq0 dq0 dq1 b10 9 a15 a15 a15 p1 47 dq4 dq9 dq35 n10 85 dnu dq4 dq9 b3 10 dnu dq14 dq25 n3 48 dq4 dq9 dq35 n10 86 dnu dq4 dq9 b3 11 dnu dq14 dq25 n3 49 dm dm dm p12 87 dnu dnu dq8 b2 12 dnu dnu dq24 n2 50 a19 a19 a19 n12 88 dnu dnu dq8 b2 13 dnu dnu dq24 n2 51 a11 a11 a11 m11 89 dnu dq5 dq11 c3 14 dnu dq15 dq23 p3 52 a12 a12 a12 m10 90 dnu dq5 dq11 c3 15 dnu dq15 dq23 p3 53 a10 a10 a10 m12 91 dnu dnu dq10 c2 16 dnu dnu dq22 p2 54 a13 a13 a13 l12 92 dnu dnu dq10 c2 17 dnu dnu dq22 p2 55 a14 a14 a14 l11 93 dnu dq6 dq13 d3 18 dnu qk1 qk1 r2 56 ba1 ba1 ba1 k11 94 dnu dq6 dq13 d3 19 dnu qk1# qk1# r3 57 ck# ck# ck# k12 95 dnu dnu dq12 d2 20 dnu dnu dq20 t2 58 ck ck ck j12 96 dnu dnu dq12 d2 21 dnu dnu dq20 t2 59 ba0 ba0 ba0 j11 97 dnu dnu dq14 e2 22 dnu dq16 dq21 t3 60 a4 a4 a4 h11 98 dnu dnu dq14 e2 23 dnu dq16 dq21 t3 61 a3 a3 a3 h12 99 dnu dq7 dq15 e3 24 dnu dnu dq18 u2 62 a0 a0 a0 g12 100 dnu dq7 dq15 e3 25 dnu dnu dq18 u2 63 a2 a2 a2 g10 101 dnu dnu dq16 f2 26 dnu dq17 dq19 u3 64 a1 a1 a1 g11 102 dnu dnu dq16 f2 27 dnu dq17 dq19 u3 65 a20 a20 (a20) e12 103 dnu dq8 dq17 f3 28 z q zq zq v2 66 qvld qvld qvld f12 104 dnu dq8 dq17 f3 29 dq8 dq13 dq27 u10 67 dq3 dq3 dq7 f10 105 a21 (a21) (a21) e1 30 dq8 dq13 dq27 u10 68 dq3 dq3 dq7 f10 106 a5 a5 a5 f1 31 dnu dnu dq26 u11 69 dnu dnu dq6 f11 107 a6 a6 a6 g2 32 dnu dnu dq26 u11 70 dnu dnu dq6 f11 108 a7 a7 a7 g3 33 dq7 dq12 dq29 t10 71 dq2 dq2 dq5 e10 109 a8 a8 a8 g1 34 dq7 dq12 dq29 t10 72 dq2 dq2 dq5 e10 110 ba2 ba2 ba2 h1 35 dnu dnu dq28 t11 73 dnu dnu dq4 e11 111 a9 a9 a9 h2 36 dnu dnu dq28 t11 74 dnu dnu dq4 e11 112 nf nf dk0# j2 37 dq6 dq11 dq31 r10 75 qk0 qk0 qk0 d11 113 nf nf dk0 j1 38 dq6 dq11 dq31 r10 76 qk0# qk0# qk0# d10 bit# bit# bit#
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 32 ordering information commercial ? range: ? t c ? = ? 0 ? to ? +95c; ? t a ? = ? 0c ? to ? +70c ? frequency ? speed ?? order ? part ? no. ? organization ? package ? 533 ? mhz ? 1.875ns ? (trc=15ns) ? is49nlc96400 \ 18b ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 18bl ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 18b ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 18bl ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 18b ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 18bl ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? 400 ? mhz ? 2.5ns ? (trc=15ns) ? is49nlc96400 \ 25eb ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 25ebl ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 25eb ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 25ebl ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 25eb ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 25ebl ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? 400 ? mhz ? 2.5ns ? (trc=20ns) ? is49nlc96400 \ 25b ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 25bl ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 25b ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 25bl ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 25b ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 25bl ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? 300 ? mhz ? 3.3ns ? (trc=20ns) ? is49nlc96400 \ 33b ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 33bl ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 33b ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 33bl ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 33b ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 33bl ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? 200 ? mhz ? 5ns ? (trc=20ns) ? is49nlc96400 \ 5b ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 5bl ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 5b ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 5bl ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 5b ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 5bl ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? note: ?? please ? contact ? issi ? for ? availability ? of ?\ 5 ? speed ? grade ? option. ? the ?\ 33 ? speed ? grade ? option ? is ? backward ? compatible ? with ? all ? timing ? specification ? for ? slower ? grades.
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 33 ordering information industrial ? range: ? t c ? = ? ? ? 40c ? to ? 95c; ? t a ? = ? ? ? 40c ? to ? +85c ? frequency ? speed ?? order ? part ? no. ? organization ? package ? 533 ? mhz ? 1.875ns ? (trc=15ns) ? is49nlc96400 \ 18bi ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 18bli ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 18bi ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 18bli ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 18bi ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 18bli ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? 400 ? mhz ? 2.5ns ? (trc=15ns) ? is49nlc96400 \ 25ebi ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 25ebli ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 25ebi ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 25ebli ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 25ebi ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 25ebli ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? 400 ? mhz ? 2.5ns ? (trc=20ns) ? is49nlc96400 \ 25bi ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 25bli ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 25bi ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 25bli ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 25bi ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 25bli ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? 300 ? mhz ? 3.3ns ? (trc=20ns) ? is49nlc96400 \ 33bi ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 33bli ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 33bi ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 33bli ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 33bi ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 33bli ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? 200 ? mhz ? 5ns ? (trc=20ns) ? is49nlc96400 \ 5bi ? 64m ? x ? 9 ? 144 ? fbga ? ?? is49nlc96400 \ 5bli ? 64m ? x ? 9 ? 144 ? fbga, ? lead \ free ? ?? IS49NLC18320 \ 5bi ? 32m ? x ? 18 ? 144 ? fbga ? ?? IS49NLC18320 \ 5bli ? 32m ? x ? 18 ? 144 ? fbga, ? lead \ free ? ?? is49nlc36160 \ 5bi ? 16m ? x ? 36 ? 144 ? fbga ? ?? is49nlc36160 \ 5bli ? 16m ? x ? 36 ? 144 ? fbga, ? lead \ free ? note: ?? please ? contact ? issi ? for ? availability ? of ?\ 5 ? speed ? grade ? option. ? the ?\ 33 ? speed ? grade ? option ? is ? backward ? compatible ? with ? all ? timing ? specification ? for ? slower ? grades. ?
is49nlc96400,IS49NLC18320,is49nlc36160 integrated silicon solution, inc. ? www.issi.com ? rev. 00e, 06/20/2012 34 ball ? grid ? array ? package ? code: ? b ? (144 \ ball) ?

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